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5
IVC102
Charge Injection
of S
2
Op Amp V
OS
+
I
IN
R
S2
0V
Integrate
(S
2
Open)
T
1
0V
S
2
V
O
T
2
10μs
Reset
10μs
Reset
I
IN
Photodiode
60pF
30pF
10pF
0.1μF
0.1μF
1
2
3
4
5
6
11
12
13
10
V
O
14
V+
+15V
Logic
High
(+5V)
S
1
C
1
C
2
C
3
S
2
Digital
Ground
Analog
Ground
S
2
9
–15V
V–
Digital
Data
Sampling
A/D
Converter
See timing
signal below
APPLICATION INFORMATION
Figure 1 shows the basic circuit connections to operate the
IVC102. Bypass capacitors are shown connected to the
power supply pins. Noisy power supplies should be avoided
or decoupled and carefully bypassed.
The Analog Ground terminal, pin 1, is shown internally
connected to the non-inverting input of the op amp. This
terminal connects to other internal circuitry and should be
connected to ground. Approximately 200
μ
A flows out of
this terminal.
Digital Ground, pin 13, should be at the same voltage
potential as analog ground (within 100mV). Analog and
Digital grounds should be connected at some point in the
system, usually at the power supply connections to the
circuit board. A separate Digital Ground is provided so that
noisy logic signals can be referenced to separate circuit
board traces.
Integrator capacitors C
1
, C
2
and C
3
are shown connected in
parallel for a total C
INT
= 100pF. The IVC102 can be used
for a wide variety of integrating current measurements. The
input signal connections and control timing and C
INT
value
will depend on the sensor or signal type and other applica-
tion details.
BASIC RESET-AND-INTEGRATE MEASUREMENT
Figure 1 shows the circuit and timing for a simple reset-and-
integrate measurement. The input current is connected di-
rectly to the inverting input of the IVC102, pin 3. Input
current is shown flowing out of pin 3, which produces a
positive-going ramp at V
O
. Current flowing into pin 3 would
produce a negative-going ramp.
A measurement cycle starts by resetting the integrator output
voltage to 0V by closing S
2
for 10
μ
s. Integration of the input
current begins when S
2
opens and the input current begins to
charge C
INT
. V
O
is measured with a sampling a/d converter
at the end of an integration period, just prior to the next reset
period. The ideal result is proportional to the average input
current (or total accumulated charge).
Switch S
2
is again closed to reset the integrator output to 0V
before the next integration period.
This simple measurement arrangement is suited to many
applications. There are, however, limitations to this basic
approach. Input current continues to flow through S
2
during
the reset period. This leaves a small voltage on C
INT
equal
to the input current times R
S2
, the on-resistance of S
2
,
approximately 1.5k
.
FIGURE 1. Reset-and Integrate Connections and Timing.
Figure 1b
Figure 1a