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參數(shù)資料
| 型號： | ISPPAC-CLK5320S-01T64I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 10/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER FANOUT ISP UNIV 64TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | ispClock™ |
| 類型： | 時鐘發(fā)生器，扇出配送，零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 輸出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:20 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（10x10） |
| 包裝： | 托盤 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
18
Figure 12. PLL Loop Bandwidth vs. Feedback Divider Setting (Nominal)
VCO
The ispClock5300S provides an internal VCO which provides an output frequency ranging from 160MHz to
400MHz. The VCO is implemented using differential circuit design techniques which minimize the inuence of
power supply noise on measured output jitter. The VCO is also used to generate output clock skew as a function of
the total VCO period. Using the VCO as the basis for controlling output skew allows for highly precise and consis-
tent skew generation, both from device-to-device, as well as channel-to-channel within the same device.
Output V Dividers
The ispClock5300S incorporates a set of three 5-bit programmable Power of 2 dividers which provide the ability to
synthesize output frequencies differing from that of the reference clock input.
Each one of the three V dividers can be independently programmed to provide division ratios ranging from 1 to 32
in Power of 2 steps (1, 2, 4, 8, 16, 32).
PLL Bandwidth vs.
VCO Frequency and V-Divider
(Standard Mode)
Dynamic Phase Offset vs.
Input Frequency and Modulation Index (MI)
(Vdiv = 2)
Dynamic Phase Offset vs.
Input Frequency and Modulation Index (MI)
(Vdiv = 4)
PLL Loop Bandwidth vs.
VCO Frequency and V-Divider
(Spread Spectrum Compatible Mode)
100
80
100 120 140 160 180 200 220 240 260
40
60
80
100
120
140
0.0
50
60
50
40
30
20
10
0
40
30
20
10
0
1.0
2.0
3.0
4.0
5.0
6.0
200
300
400
500
Vdiv=1
Vdiv=2
Vdiv=4
Vdiv=8
Vdiv=16
Vdiv=32
MI = 0.25%
MI = 0.50%
MI = 1.0%
MI = 2.0%
Vdiv=32
Vdiv=16
Vdiv=8
Vdiv=4
Vdiv=2
Band
width
(MHz)
VCO Frequency (MHz)
100
200
300
400
500
600
VCO Frequency (MHz)
Input Frequency (MHz)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Band
width
(MHz)
T
PDJ
(ps
RMS)
T
PDJ
(ps
RMS)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5320S-01T64I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5320S-01TN48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5320S-01TN48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5320S-01TN64C | 功能描述:時鐘驅(qū)動器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5320S-01TN64C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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