Specifications ispLSI 1048E 12 USE ispLSI 1048EA FOR NEW DESIGNS Maximum GRP Delay vs. GLB Loads 3 1 8 16 32 GLB Loads GRP Delay (ns) 2 1 4 5 6" />
參數(shù)資料
型號(hào): ISPLSI 1048E-70LQNI
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 4/17頁(yè)
文件大小: 0K
描述: IC PLD ISP 96I/O 15NS 128PQFP
標(biāo)準(zhǔn)包裝: 24
系列: ispLSI® 1000E
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 15.0ns
電壓電源 - 內(nèi)部: 4.5 V ~ 5.5 V
邏輯元件/邏輯塊數(shù)目: 48
門數(shù): 8000
輸入/輸出數(shù): 96
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-BQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(28x28)
包裝: 托盤
其它名稱: 220-1599
ISPLSI 1048E-70LQNI-ND
ISPLSI1048E-70LQNI
Specifications ispLSI 1048E
12
USE
ispLSI
1048EA
FOR
NEW
DESIGNS
Maximum GRP Delay vs. GLB Loads
3
1
8
16
32
GLB Loads
GRP
Delay
(ns)
2
1
4
5
6
7
4
0127A/1048E
8
48
ispLSI 1048E-50
ispLSI 1048E-70
ispLSI 1048E-90/100
ispLSI 1048E-125
9
10
ICC can be estimated for the ispLSI 1048E using the following equation:
ICC = 20 + (# of PTs * 0.42) + (# of nets * Max. freq * 0.010)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 4 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
0127B/1048E
Notes: Configuration of twelve 16-bit counters,
Typical current at 5V, 25°C
180
220
260
300
340
380
0
20
40
60
80
100
120
140
fmax (MHz)
I CC
(mA)
ispLSI 1048E
Power Consumption
Power consumption in the ispLSI 1048E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
Figure 3 shows the relationship between power and
operating speed.
Figure 3. Typical Device Power Consumption vs fmax
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