參數(shù)資料
型號(hào)： ISP1183
廠商： NXP Semiconductors N.V.
英文描述： Low-power Universal Serial Bus interface device with DMA
中文描述： 低功耗通用串行總線與DMA接口設(shè)備
文件頁(yè)數(shù)： 29/62頁(yè)
文件大小： 295K
代理商： ISP1183
Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
Product data
Rev. 01 — 24 February 2004
29 of 62
9397 750 11804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.1.3
Mode register (R/W: B9H/B8H)
This command accesses the ISP1183 Mode register, which consists of 1 byte (bit
allocation: see
Table 18
). In the 16-bit bus mode, the upper byte is ignored.
The Mode register controls the DMA bus width, resume and suspend modes,
interrupt activity and SoftConnect operation. It can be used to enable debug mode, in
which all errors and Not Acknowledge (NAK) conditions will generate an interrupt.
Code (hex): B8/B9 —
write or read Mode register
Transaction —
write or read 1 byte
[1]
Unchanged by a bus reset.
13.1.4
Hardware Configuration register (R/W: BBH/BAH)
This command accesses the Hardware Configuration register that consists of
2 bytes. The first (lower) byte contains the device configuration and control values,
the second (upper) byte holds the clock control bits and the clock division factor. The
bit allocation is given in
Table 20
. A bus reset will not change any of the programmed
bit values.
The Hardware Configuration register controls the connection to the USB bus, clock
activity and power supply during the suspend state, output clock frequency, DMA
operating mode and pin configurations (polarity, signaling mode).
Code (hex): BA/BB —
write or read Hardware Configuration register
Transaction —
write or read 2 bytes
Table 18:
Bit
Symbol
Reset
Access
Mode register: bit allocation
7
reserved
0
[1]
R/W
6
5
4
3
2
1
0
reserved
0
R/W
GOSUSP
0
R/W
reserved
0
R/W
INTENA
0
[1]
R/W
DBGMOD
0
[1]
R/W
reserved
0
[1]
R/W
SOFTCT
0
[1]
R/W
Table 19:
Bit
7
6
5
4
3
2
Mode register: bit description
Symbol
Description
reserved
This bit should be always written as logic 0.
-
reserved
GOSUSP
Writing logic 1 followed by logic 0 will activate the suspend mode.
-
reserved
INTENA
Logic 1 enables all interrupts. Bus reset value: unchanged.
DBGMOD
Logic 1 enables the debug mode, in which all NAKs and errors
will generate an interrupt. Logic 0 selects normal operation, in
which interrupts are generated on every ACK (bulk endpoints) or
after every data transfer (isochronous endpoints). Bus reset
value: unchanged.
-
reserved
SOFTCT
Logic 1 enables SoftConnect (see
Section 8.4
). This bit is ignored
if EXTPUL = 1 in the Hardware Configuration register (see
Table 20
). Bus reset value: unchanged.
1
0
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