參數(shù)資料
型號: ISP1161BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 58/127頁
文件大?。?/td> 2762K
代理商: ISP1161BM
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
58 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
13.1.4
HcInterruptStatus Register
This register provides the status of the events that cause hardware interrupts. When
an event occurs, the HC sets the corresponding bit in this register. When a bit
becomes set, a hardware interrupt is generated if the interrupt is enabled in the
HcInterruptEnable register (see
Section 13.1.5
) and the MasterInterruptEnable bit is
set. The HCD may clear specific bits in this register by writing logic1 to the bit
positions to be cleared. The HCD may not set any of these bits. The HC will not clear
the bit.
Table 22: HcInteruptStatus Register: bit allocation
Bit
31
Symbol
Reset
Access
Bit
23
Symbol
Reset
Access
Bit
15
Symbol
Reset
Access
Bit
7
Symbol
reserved
Reset
0
Access
30
29
28
27
26
25
24
reserved
00H
R/W
22
21
20
19
18
17
16
reserved
00H
R/W
14
13
12
11
10
9
8
reserved
00H
R/W
6
5
4
3
2
1
0
RHSC
0
FNO
0
UE
0
RD
0
SF
0
reserved
0
SO
0
R/W
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