參數(shù)資料
型號: ISP1161BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 16/127頁
文件大?。?/td> 2762K
代理商: ISP1161BM
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
16 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
For ISP1161’s ES1 (engineering sample: version one), the chip’s ID is 6110H, where
the upper byte of 61H stands for ISP1161, and the lower byte of 10H stands for the
first version of the IC chip.
Most of ISP1161’s internal control registers are 16 bits wide. Some of the internal
control registers, however, have 32-bit width.
Figure 14
shows how ISP1161’s 32-bit
internal control register is accessed. The complete cycle of accessing a 32-bit
register consists of a command phase followed by two data phases. In the two data
phases, the microprocessor should first read or write the lower 16-bit data, followed
by the upper 16-bit data.
To further describe the complete access cycles of ISP1161’s internal control
registers, the status of some pin signals of the microprocessor bus interface are
shown in
Figure 15
and
Figure 16
for the HC and the DC respectively.
Fig 13. 16-bit register access cycle.
Fig 14. 32-bit register access cycle.
Fig 15. Accessing ISP1161 HC control registers.
MGT937
read/write data
(16 bits)
16-bit register access cycle
t
write command
(16 bits)
MGT938
read/write data
(lower 16 bits)
32-bit register access cycle
t
read/write data
(upper 16 bits)
write command
(16 bits)
Signals
Valid status
0
01
CS
A1, A0
Valid status
0
00
Valid status
0
00
RD, WR
RD = 1,
WR = 0
RD = 0 (read) or
WR = 0 (write)
data bus
Command code
Register data
(upper word)
Register data
(lower word)
RD = 0 (read) or
WR = 0 (write)
MGT939
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