參數(shù)資料
型號(hào): ISP1160
廠商: NXP Semiconductors N.V.
英文描述: Embedded Universal Serial Bus Host Controller
中文描述: 嵌入式通用串行總線主控制器
文件頁(yè)數(shù): 6/88頁(yè)
文件大小: 2044K
代理商: ISP1160
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 04 — 04 July 2003
6 of 88
9397 750 11371
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
DACK_N
27
I
HC DMA acknowledge input; when not in use, this pin must
be connected to V
CC
via an external 10 k
resistor
this pin must be connected to V
CC
via an external 10 k
resistor
HC interrupt output; programmable level, edge triggered
and polarity; see
Section 10.4.1
no connection; leave this pin open
no connection; leave this pin open
reset input (Schmitt trigger); a LOW level produces an
asynchronous reset (internal pull-up resistor)
indicates to the HC software the Number of Downstream
Ports (NDP) present:
TEST_HIGH
28
-
INT
29
O
n.c.
n.c.
RESET_N
30
31
32
-
O
I
NDP_SEL
33
I
0 —
select 1 downstream port
1 —
select 2 downstream ports
only changes the value of the NDP field in the
HcRhDescriptorA register; both ports will always be
enabled; see
Section 10.3.1
(internal pull-up resistor)
DMA master device to inform the ISP1160 of end of DMA
transfer; active level is programmable; when not in use, this
pin must be connected to V
CC
via an external 10 k
resistor; see
Section 10.4.1
digital ground
no connection; leave this pin open
this pin must be connected to DGND via an external 10 k
resistor
no connection; leave this pin open
this pin must be connected to DGND via a 1 M
resistor
HC wake-up input; generates a remote wake-up from the
suspend state (active HIGH); when not in use, this pin must
be connected to DGND via an external 10 k
resistor
(internal pull-down resistor)
no connection; leave this pin open
HC suspend state indicator output; active HIGH
crystal input; connected directly to a 6 MHz crystal; when
this pin is connected to an external clock source,
pin XTAL2 must be left open
crystal output; connected directly to a 6 MHz crystal; when
pin XTAL1 is connected to an external clock source, this
pin must be left open
digital ground
power switching control output for downstream port 1;
open-drain output
power switching control output for downstream port 2;
open-drain output
EOT
34
I
DGND
n.c.
TEST_LOW
35
36
37
-
-
-
n.c.
TEST_LOW
H_WAKEUP
38
39
40
-
-
I
n.c.
H_SUSPEND
XTAL1
41
42
43
-
O
I
XTAL2
44
O
DGND
H_PSW1_N
45
46
-
O
H_PSW2_N
47
O
Table 2:
Symbol
[1]
Pin description for LQFP64
…continued
Pin
Type
Description
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