參數(shù)資料
型號(hào)： ISP1130DL
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Universal Serial Bus compound hub with integrated keyboard controller
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56
封裝： PLASTIC, SSOP-56
文件頁數(shù)： 49/68頁
文件大小： 1786K
代理商： ISP1130DL
Philips Semiconductors
ISP1130
USB compound hub with keyboard controller
Objective specification
Rev. 01 — 23 March 2000
49 of 68
9397 750 06895
Philips Electronics N.V. 2000. All rights reserved.
[1]
All bits are individually addressable.
[1]
Bits are transmitted or received MSB (SD7) first.
I2C0CON.2
AA
Assert Acknowledge
. A logic 1 indicates that an ACK (low
level on SDA during acknowledge pulse on SCL) is returned
for one of the following conditions:
own slave address received
General Call address received, if bit GC = 1 (I2C0CON)
data byte received when in master receive mode
data byte received when addressed in slave receiver
mode.
selects I
2
C-bus bit frequency in Master mode, see
Table 78
selects I
2
C-bus bit frequency in Master mode, see
Table 78
I2C0CON.1
I2C0CON.0
CR1
CR0
Table 78: I
2
C-bus bit frequency (Master mode)
CR2
CR1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
CR0
0
1
0
1
0
1
0
1
I
2
C-bus bit frequency (12 MHz oscillator)
200 kHz
7.5 kHz
300 kHz
400 kHz
50 kHz
3.75 kHz
75 kHz
100 kHz
Table 77: I2C0CON register: bit description
…continued
Bit
[1]
Symbol
Description
Table 79: I2C0DAT register: bit allocation
Bit
7
Symbol
Reset
0
Access
R/W
6
5
4
3
2
1
0
SD[7:0]
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 80: I2C0DAT register: bit description
Bit
Symbol
7 to 0
SD[7:0]
[1]
Description
DATA byte (just received or to be transmitted); a logic 0 value
corresponds with a LOW level on SDA, a logic 1 with a HIGH
level
Table 81: I2C0STA register: bit allocation
Bit
7
Symbol
Reset
1
Access
R
6
5
4
3
2
-
0
R
1
-
0
R
0
-
0
R
SC[4:0]
1
R
1
R
1
R
1
R
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