參數(shù)資料
型號： ISP1109BS
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： Universal Serial Bus transceiver with carkit support
中文描述： LINE TRANSCEIVER, PQCC32
封裝： LEAD FREE, 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT617-1, HVQFN-32
文件頁數(shù)： 23/59頁
文件大小： 295K
代理商： ISP1109BS
9397 750 13355
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
23 of 59
Philips Semiconductors
ISP1109
USB transceiver with carkit support
9.1.2.4
Timer Control register (S/C: 18h/19h)
The bit allocation of the Timer Control register is given in
Table 25
.
9.1.2.5
Resistor Control register
Table 27
shows the bit allocation of the Resistor Control register.
4
ISET_STATE
Determines the logic level for pin ISET when bit ISET_DRV_EN is
logic 1.
0 —
ISET outputs LOW
1 —
ISET outputs HIGH.
Enables software control of the state of pin ISET:
0 —
Disable; the ISET output will be controlled by hardware
1 —
Enable; the ISET output will be controlled by bit ISET_STATE.
Audio loopback test:
0 —
Turn off the switch between the MIC and SPKR_R pins
1 —
Turn on the switch between the MIC and SPKR_R pins.
Audio loopback test:
0 —
Turn off the switch between the MIC and SPKR_L pins
1 —
Turn on the switch between the MIC and SPKR_L pins.
Selection between stereo and mono audio modes:
0 —
Stereo mode: SPKR_L
DM, SPKR_R
DP
1 —
Mono mode: SPKR_L
DM, MIC
DP.
3
ISET_DRV_EN
2
SW_MIC_
SPKR_R
1
SW_MIC_
SPKR_L
0
AUDIO_MONO
Table 24:
Bit
Audio Control register (address Set = 16h, Clear = 17h) bit description
…continued
Symbol
Description
Table 25:
Bit
Symbol
Reset
Access
Timer Control register (address Set = 18h, Clear = 19h) bit allocation
7
6
5
TMR_SE1[3:0]
0
0
0
R/S/C
R/S/C
R/S/C
4
3
2
1
0
reserved
1
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 26:
Bit
7 to 4
Timer Control register (address Set = 18h, Clear = 19h) bit description
Symbol
Description
TMR_SE1[3:0]
Program the timer value to detect SE1 on the DP and DM lines. The
interval is 1 ms (Default value = 1 ms).
-
reserved
3 to 0
Table 27:
Bit
Symbol
Resistor Control register (address Set = 06h, Clear = 07h) bit allocation
7
6
5
VBUS_
CHRG
DISCHRG
0
0
0
R/S/C
R/S/C
R/S/C
4
3
2
1
0
VBUS_
reserved
ID_PULL
DN
0
R/S/C
DM_PULL
DOWN
0
R/S/C
DP_PULL
DOWN
0
R/S/C
DP_WKPU
_EN
1
R/S/C
DP_PULL
UP
1
R/S/C
Reset
Access
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