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參數(shù)資料
| 型號： | ISL98003INZ-110 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 17/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AFE 3CH 8BIT 110MHZ 80EPTQFP |
| 標準包裝： | 119 |
| 位數(shù)： | 8 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 1.1W |
| 電壓 - 電源，模擬： | 1.8V，3.3V |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 2 V |
| 封裝/外殼： | 80-TQFP 裸露焊盤 |
| 供應商設備封裝： | 80-TQFP-EP（12x12） |
| 包裝： | 托盤 |
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24
FN6760.0
September 12, 2008
Intersil’s DPLL has the capability to correct large phase
changes almost instantly by maximizing the phase error gain
while keeping the frequency gain relatively low. This is done
by changing the contents of register 0x74 to 0x4C. This
increases the phase error gain to 100%. Because a phase
setting, this high will slightly increase jitter, the default setting
(0x49) for register 0x74 is recommended for all other sync
sources.
Sync Timing Measurement
The ISL98003 analyzes the timing characteristics of the sync
signals for the currently selected input channel and presents
the results in registers 0x40 through 0x46.
The HSYNC period and pulse width values are 16-bit
numbers representing the number of crystal clocks in 16
consecutive periods or pulse widths giving a measurement
resolution of 1/16th of a crystal clock.
The VSYNC period is a 12-bit number representing the
number of either HSYNCs or units of 512 crystal clocks that
occur in one video frame. The default is to count HSYNC
pulses, but setting register 0x4F[0] = 1 changes to the units
to crystal clock/512.
The VSYNC pulse width is a 12-bit number representing the
number of either HSYNCs or units of 512 crystal clocks that
occur in one VSYNC. The default is to count HSYNC pulses,
but setting register 0x4F[0] = 1 changes to the units to
crystal clock/512.
PGA
The ISL98003’s Programmable Gain Amplifier (PGA) has a
nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB).
The transfer function is shown in Equation 1:
where GainCode is the value in the Gain register for that
particular color. Note that for a gain of 1V/V, the GainCode
should be 85 (0x55). This is a different center value than the
128 (0x80) value used by some other AFEs, so the firmware
should take this into account when adjusting gains.
The PGAs are updated by the internal clamp signal once per
line. In normal operation this means that there is a maximum
delay of one HSYNC period between a write to a Gain
register for a particular color and the corresponding change
in that channel’s actual PGA gain. If there is no regular
HSYNC/SOG source, or if the external clamp option is
enabled (register 0x10[7:6]) but there is no external clamp
signal being generated, it may take up to 100ms for a write
to the Gain register to update the PGA. This is not an issue
in normal operation with RGB and YPbPr signals.
Offset DAC
The ISL98003 features a 10-bit Digital-to-Analog Converter
(DAC) to provide extremely fine control over the full channel
offset. The DAC is placed after the PGA to eliminate
interaction between the PGA (controlling “contrast”) and the
Offset DAC (controlling “brightness”).
In normal operation, the Offset DAC is controlled by the
ABLC circuit, ensuring that the offset is always reduced to
sub-LSB levels (see “Automatic Black Level Compensation
(ABLC)” on page 25 for more information). When ABLC is
enabled, the Offset register pairs (0x18 - 0x19, 0x1A -0x1B
and 0x1C - 0x1D) control a digital offset added to or
subtracted from the output of the ADC. This mode provides
the best image quality and eliminates the need for any
offset calibration.
If desired, ABLC can be disabled (0x27[0] = 1) and the
Offset DAC programmed manually, with the 8 most
significant bits in registers 0x18, 0x1A,10x1C, and the 2
least significant bits in registers 0x19[7:6], 0x1B[7:6] and
0x1D[7:6].
-
+
GREEN
SLICER DAC
600mV TO 900mV
+
–
600m V
SOGIN
1A
4
RIN
CIN
10nF
500
CLAM P
SLICE
FILTER
ON/OFF
HIST
ON/OFF
-
+
SYNCOUT
FIGURE 2. SOG SLICER
Ω
Gain
V
----
0.5
GainCode
170
-----------------------------
+
=
(EQ. 1)
ISL98003
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