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參數(shù)資料
| 型號： | ISL98001CQZ-210 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 15/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRPL VIDEO DIGITIZER 128-MQFP |
| 標準包裝： | 660 |
| 類型： | 視頻數(shù)字轉(zhuǎn)換器 |
| 應(yīng)用： | 數(shù)字電視，顯示器，數(shù)字 KVM，圖形處理 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
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22
FN6148.5
September 21, 2010
PGA
The ISL98001’s Programmable Gain Amplifier (PGA) has a
nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB).
The transfer function is in Equation 1:
where GainCode is the value in the Gain register for that
particular color. Note that for a gain of 1V/V, the GainCode
should be 85 (0x55). This is a different center value than the
128 (0x80) value used by some other AFEs, so the firmware
should take this into account when adjusting gains.
The PGAs are updated by the internal clamp signal once per
line. In normal operation this means that there is a maximum
delay of one HSYNC period between a write to a Gain
register for a particular color and the corresponding change
in that channel’s actual PGA gain. If there is no regular
HSYNC/SOG source, or if the external clamp option is
enabled (register 0x13[5:4]) but there is no external clamp
signal being generated, it may take up to 100ms for a write
to the Gain register to update the PGA. This is not an issue
in normal operation with RGB and YPbPr signals.
Bandwidth and Peaking Control
Register 0x0D[3:1] controls a low pass filter allowing the
input bandwidth to be adjusted with three bit resolution
between its default value (0x0E = 780MHz) and its minimum
bandwidth (0x00, for 100MHz). Typically the higher the
resolution, the higher the desired input bandwidth. To
minimize noise, video signals should be digitized with the
minimum bandwidth setting that passes sharp edges.
Table 4 shows the corner frequencies for different register
settings.
Register 0x0D[7:4] controls a programmable zero, allowing
high frequencies to be boosted, restoring some of the
harmonics lost due to excessive EMI filtering, cable losses, etc.
This control has a very large range, and can introduce high
frequency noise into the image, so it should be used judiciously,
or as an advanced user adjustment.
Table 5 shows the corner frequency of the zero for different
peaking register settings. Values above 0x2 may cause
excessive noise, depending on the quality of the input signal
and the PCB environment.
Offset DAC
The ISL98001 features a 10-bit Digital-to-Analog Converter
(DAC) to provide extremely fine control over the full channel
offset. The DAC is placed after the PGA to eliminate
interaction between the PGA (controlling “contrast”) and the
Offset DAC (controlling “brightness”).
In normal operation, the Offset DAC is controlled by the
ABLC circuit, ensuring that the offset is always reduced to
sub-LSB levels (See“Automatic Black Level Compensation
(ABLC)” on page 23). When ABLC is enabled, the Offset
registers (0x09, 0x0A, 0x0B) control a digital offset added
to or subtracted from the output of the ADC. This mode
provides the best image quality and eliminates the need for
any offset calibration.
If desired, ABLC can be disabled (0x17[0] = 1) and the
Offset DAC programmed manually, with the 8 most
TABLE 4. BANDWIDTH CONTROL
0x0D[3:0] VALUE
(LSB = “x” = “don’t care”)
AFE BANDWIDTH
000x
100MHz
001x
130MHz
010x
150MHz
011x
180MHz
100x
230MHz
101x
320MHz
110x
480MHz
111x
780MHz
Gain
V
----
0.5 GainCode
170
-----------------------------
+
=
(EQ. 1)
TABLE 5. PEAKING CORNER FREQUENCIES
0X0D[7:4] VALUE
ZERO CORNER FREQUENCY
0x0
Peaking disabled
0x1
800MHz
0x2
400MHz
0x3
265MHz
0x4
200MHz
0x5
160MHz
0x6
135MHz
0x7
115MHz
0x8
100MHz
0x9
90MHz
0xA
80MHz
0xB
70MHz
0xC
65MHz
0xD
60MHz
0xE
55MHz
0xF
50MHz
ISL98001
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