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參數(shù)資料
| 型號： | ISL98001CQZ-210 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 14/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRPL VIDEO DIGITIZER 128-MQFP |
| 標準包裝： | 660 |
| 類型： | 視頻數(shù)字轉(zhuǎn)換器 |
| 應(yīng)用： | 數(shù)字電視，顯示器，數(shù)字 KVM，圖形處理 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
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21
FN6148.5
September 21, 2010
the HSYNC input, or composite sync from a Sync-On-Green
(SOG) signal embedded on the Green video input. The
ISL98001 has SYNC activity detect functions to help the
firmware determine which sync source is available.
Macrovision
The ISL98001 automatically detects the presence of
Macrovision-encoded video. When Macrovision is detected,
it generates a mask signal that is ANDed with the incoming
SOG CSYNC signal to remove the Macrovision before the
HSYNC goes to the PLL. No additional programming is
required to support Macrovision.
If desired (it is never necessary in normal operation), this
function can be disabled by setting the Sync Mask Disable
(register 0x05 bit 6) to a 1.
The mask signal is also applied to the HSYNCOUT signal.
When Sync Mask Disable = 0, any Macrovision present on
the incoming sync will not be visible on HSYNCOUT. If the
application requires the Macrovision pulses to be visible on
HSYNCOUT, set the HSYNCOUT Mask Disable bit (register
0x05 bit 7).
Headswitching from Analog Videotape Signals
Occasionally this AFE may be used to digitize signals
coming from analog videotape sources. The most common
example of this is a Digital VCR (which for best signal quality
would be connected to this AFE with a component YPbPr
connection). If the digital VCR is playing an older analog
VHS tape, the sync signals from the VCR may contain the
worst of the traditional analog tape artifacts: headswitching.
Headswitching is traditionally the enemy of PLLs with large
capture ranges, because a headswitch can cause the
HSYNC period to change by as much as ±90%. To the PLL,
this can look like a frequency change of -50% to greater than
+900%, causing errors in the output frequency (and
obviously the phase) to change. Subsequent HSYNCs have
the correct, original period, but most analog PLLs will take
dozens of lines to settle back to the correct frequency and
phase after a headswitch disturbance. This causes the top of
the image to “tear” during normal playback. In “trick modes”
(fast forward and rewind), the HSYNC signal has multiple
headswitch-like discontinuities, and many PLLs never settle
to the correct value before the next headswitch, rendering
the image completely unintelligible.
Intersil’s DPLL has the capability to correct large phase
changes almost instantly by maximizing the phase error gain
while keeping the frequency gain relatively low. This is done
by changing the contents of register 0x1C to 0x4C. This
increases the phase error gain to 100%. Because a phase
setting this high will slightly increase jitter, the default setting
(0x49) for register 0x1C is recommended for all other sync
sources.
0:
VGA1
0x05[0]
1:
VGA2
HSYNCIN1
HSYNC1
SLICER
0x03[2:0]
VSYNCIN1
SOGIN1
HSYNC2
SLICER
0x03[6:4]
HSYNCIN
VSYNCIN
ACTIVITY 0x01[6:0]
&
POLARITY 0x02[5:0]
DETECT
HSYNCIN2
VSYNCIN2
SOGIN2
SYNC
SPLITTER
PLL
0x0E through 0x13
HSYNCOUT
VSYNCOUT
COAST
GENERATION
0x11, 0x12
XTALIN
XTALOUT
0: ÷1
0x13
[6]
1: ÷2
÷2
XTALCLOCKOUT
Output
Formatter
0x18,
0x19,
0x1A
Pixel Data
from AFE
24
RP[7:0]
RS[7:0]
GP[7:0]
GS[7:0]
BP[7:0]
BS[7:0]
DATACLK
HSOUT
VSOUT
SOGIN
SOG
SLICER
0x04[3:0]
SOG
SLICER
0x04[3:0]
00, 10,
11:
HSYNCIN
0x05[4:3]
01:
SOGIN
1:
SYNC
SPLTR
0x05[3]
0:
VSYNCIN
CLOCKINVIN
HS
PIXCLK
CSYNC
SOURCE
SYNC
TYPE
VSYNC
DATACLK
FIGURE 8. SYNC FLOW
ISL98001
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