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參數(shù)資料
| 型號： | ISL98001CQZ-140 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 16/31頁 |
| 文件大小： | 0K |
| 描述： | IC TRPL VIDEO DIGITIZER 128-MQFP |
| 標準包裝： | 66 |
| 類型： | 視頻數(shù)字轉換器 |
| 應用： | 數(shù)字電視，顯示器，數(shù)字 KVM，圖形處理 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應商設備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 1247 (CN2011-ZH PDF) |
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23
FN6148.5
September 21, 2010
significant bits in registers 0x09, 0x0A, 0x0B, and the 2 least
significant bits in register 0x0C[7:2].
The default Offset DAC range is ±127 ADC LSBs. Setting
0x0C[0] = 1 reduces the swing of the Offset DAC by 50%,
making 1 Offset DAC LSB the weight of 1/8th of an ADC
LSB. This provides the finest offset control and applies to
both ABLC and manual modes.
Automatic Black Level Compensation (ABLC)
ABLC is a function that continuously removes all offset
errors from the incoming video signal by monitoring the
offset at the output of the ADC and servoing the 10-bit
analog DAC to force those errors to zero. When ABLC is
enabled, the user offset control is a digital adder, with 8-bit
resolution (refer to Table 6).
When the ABLC function is enabled (0x17[0] = 0), the ABLC
function is executed every line after the trailing edge of
HSYNC. If register 0x05[5] = 0 (the default), the ABLC
function will be not be triggered while the DPLL is coasting,
preventing any composite sync edges, equalization pulses,
or Macrovision signals from corrupting the black data and
potentially adding a small error in the ABLC accumulator.
After the trailing edge of HSYNC, the start of ABLC is
delayed by the number of pixels specified in registers 0x14
and 0x15. After that delay, the number of pixels specified
by register 0x17[3:2] are averaged together and added to
the ABLC’s accumulator. The accumulator stores the
average black levels for the number of lines specified by
register 0x17[6:4], which is then used to generate a 10-bit
DAC value.
The default values provide excellent results with offset
stability and absolute accuracy better than 1 ADC LSB for
most input signals.
ADC
The ISL98001 features 3 fully differential, high-speed 8-bit
ADCs.
Clock Generation
A Digital Phase Lock Loop (DPLL) is employed to generate
the pixel clock frequency. The HSYNC input and the external
XTAL provide a reference frequency to the PLL. The PLL
then generates the pixel clock frequency that equal to the
incoming HSYNC frequency times the HTOTAL value
programmed into registers 0x0E and 0x0F.
The stability of the clock is very important and correlates
directly with the quality of the image. During each pixel time
transition, there is a small window where the signal is
slewing from the old pixel amplitude and settling to the new
pixel value. At higher frequencies, the pixel time transitions
at a faster rate, which makes the stable pixel time even
smaller. Any jitter in the pixel clock reduces the effective
stable pixel time and thus the sample window in which pixel
sampling can be made accurately.
Sampling Phase
The ISL98001 provides 64 low-jitter phase choices per pixel
period, allowing the firmware to precisely select the optimum
sampling point. The sampling phase register is 0x10.
External Pixel Clock
The ISL98001 can bypass the PLL and use an external clock
signal to drive the ADCs but when this is done the
programmable sample phase is not available. When bits
[5:4] of register 0x13 are set to 11 a clock signal on the
CLOCKINVIN pin is used.
HSYNC Slicer
To further minimize jitter, the HSYNC inputs are treated as
analog signals, and brought into a precision slicer block with
thresholds programmable in 400mV steps with 240mV of
hysteresis, and a subsequent digital glitch filter that ignores
any HSYNC transitions within 100ns of the initial transition.
This processing greatly increases the AFE’s rejection of
ringing and reflections on the HSYNC line and allows the
AFE to perform well even with pathological HSYNC signals.
Voltages given above and in the HSYNC Slicer register
description are with respect to a 3.3V sync signal at the
HSYNCIN input pin. To achieve 5V compatibility, a 680Ω
series resistor should be placed between the HSYNC source
and the HSYNCIN input pin. Relative to a 5V input, the
hysteresis will be 240mV*5V/3.3V = 360mV, and the slicer
step size will be 400mV*5V/3.3V = 600mV per step.
TABLE 6. OFFSET DAC RANGE AND OFFSET DAC ADJUSTMENT
OFFSET
DAC RANGE
0X0C[0]
10-BIT
OFFSET DAC
RESOLUTION
ABLC
0x17[0]
USER OFFSET CONTROL RESOLUTION
USING REGISTERS 0x09 - 0X0B ONLY
(8-BIT OFFSET CONTROL)
USER OFFSET CONTROL RESOLUTION
USING REGISTERS 0X09 - 0x0B AND
0X0C[7:2](10-BIT OFFSET CONTROL)
0
0.25 ADC LSBs
(0.68mV)
0
(ABLC on)
1 ADC LSB
(digital offset control)
N/A
1
0.125 ADC LSBs
(0.34mV)
0
(ABLC on)
1 ADC LSB
(digital offset control)
N/A
0
0.25 ADC LSBs
(0.68mV)
1
(ABLC off)
1.0 ADC LSB
(analog offset control)
0.25 ADC LSB
(analog offset control)
1
0.125 ADC LSBs
(0.34mV)
1
(ABLC off)
0.5 ADC LSB
(analog offset control)
0.125 ADC LSB
(analog offset control)
ISL98001
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