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參數(shù)資料
| 型號： | ISL98001CQZ-140 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 13/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRPL VIDEO DIGITIZER 128-MQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 類型： | 視頻數(shù)字轉(zhuǎn)換器 |
| 應(yīng)用： | 數(shù)字電視，顯示器，數(shù)字 KVM，圖形處理 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-MQFP（14x20） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1247 (CN2011-ZH PDF) |
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20
FN6148.5
September 21, 2010
The ISL98001 can optionally decimate the incoming data to
provide a 4:2:2 output stream (configuration register
0x18[4] = 1) as shown in Table 2.
There is also a “compatibility mode”, enabled by setting bit 3
of register 0x18 to a 1, that outputs the U and V data with the
format used by the previous generation (“X980xx”) series of
AFEs, shown in Table 3.
Input Coupling
Inputs can be either AC-coupled (default) or DC-coupled (See
register 0x05[1]). AC coupling is usually preferred since it
allows video signals with substantial DC offsets to be accurately
digitized. The ISL98001 provides a complete internal
DC-restore function, including the DC restore clamp (See
Figure 7) and programmable clamp timing (registers 0x14,
0x15, 0x16, and 0x23).
When AC-coupled, the DC restore clamp is applied every line,
a programmable number of pixels after the trailing edge of
HSYNC. If register 0x05[5] = 0 (the default), the clamp will not
be applied while the DPLL is coasting, preventing any clamp
voltage errors from composite sync edges, equalization pulses,
or Macrovision signals.
After the trailing edge of HSYNC, the DC restore clamp is
turned on after the number of pixels specified in the DC Restore
and ABLC Starting Pixel registers (0x14 and 0x15) has been
reached. The clamp is applied for the number of pixels
specified by the DC Restore Clamp Width Register (0x16). The
clamp can be applied to the back porch of the video, or to the
front porch (by increasing the DC Restore and ABLC Starting
Pixel registers so all the active video pixels are skipped).
If DC-coupled operation is desired, the input to the ADC will be
the difference between the input signal (RIN1, for example) and
that channel’s ground reference (RGBGND1 in that example).
SOG
For component YPbPr signals, the sync signal is embedded
on the Y channel’s video, which is connected to the green
input, hence the name SOG (Sync on Green). The horizontal
sync information is encoded onto the video input by adding
the sync tip during the blanking interval. The sync tip level is
typically 0.3V below the video black level.
To minimize the loading on the Green channel, the SOG input
for each of the green channels should be AC-coupled to the
ISL98001 through a series combination of a 10nF capacitor
and a 500
Ω resistor. Inside the ISL98001, a window
comparator compares the SOG signal with an internal 4-bit
programmable threshold level reference ranging from 0mV to
300mV below the minimum sync level. The SOG threshold
level, hysteresis, and low-pass filter is programmed via
register 0x04. If the Sync-On-Green function is not needed,
the SOGIN pin(s) may be left unconnected.
SYNC Processing
The ISL98001 can process sync signals from 3 different
sources: discrete HSYNC and VSYNC, composite sync on
TABLE 2. YUV MAPPING (4:2:2)
INPUT
SIGNAL
ISL98001
INPUT
CHANNEL
ISL98001
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y
Green
Y0Y1Y2Y3
Pb
Blue
driven low
Pr
Red
U0V0U2V2
TABLE 3. YUV MAPPING (4:2:2)
INPUT
SIGNAL
ISL98001
INPUT
CHANNEL
ISL98001
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y
Green
Y0Y1Y2Y3
Pb
Blue
driven low
Pr
Red
U0V1U2V3
R(GB)IN1
CLAMP
GENERATION
R(GB)GND1
R(GB)IN2
R(GB)GND2
VGA1
VGA2
VIN+
VIN-
DC Restore
Clamp DAC
VCLAMP
8 bit ADC
Offset
DAC
Fixed
Offset
ABLC
Offset
Control
Registers
ABLC
Fixed
Offset
0x00
To
ABLC
Block
To Output
Formatter
10
8
Automatic Black Level
Compensation (ABLC) Loop
DC Restoration
Input
Bandwidth
PGA
Bandwidth
Control
8
FIGURE 7. VIDEO FLOW (INCLUDING ABLC)
ISL98001
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