參數(shù)資料
型號: ISL9305IRTWLNCZ-T
廠商: Intersil
文件頁數(shù): 7/17頁
文件大?。?/td> 771K
描述: IC REG QD BUCK/LINEAR 16TQFN
產(chǎn)品培訓(xùn)模塊: Patient Monitoring and Diagnostic Equipment Solutions
標(biāo)準(zhǔn)包裝: 6,000
拓?fù)洌?/td> 降壓(降壓)(2),線性(LDO)(2)
功能: 任何功能
輸出數(shù): 4
頻率 - 開關(guān): 3MHz
電壓/電流 - 輸出 1: 0.8 V ~ 5.5 V,800mA
電壓/電流 - 輸出 2: 0.8 V ~ 5.5 V,800mA
電壓/電流 - 輸出 3: 0.9 V ~ 3.3 V,350mA
帶 LED 驅(qū)動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 1.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-WQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-TQFN-EP(4x4)
包裝: 帶卷 (TR)
ISL9305
7
FN7605.1
August 15, 2011
Theory of Operation
DCD1 and DCD2 Introduction
Both the DCD1 and DCD2 converters on ISL9305 use the
peak-current-mode pulse-width modulation (PWM) control scheme
for fast transient response and pulse-by-pulse current limiting.
Both converters are able to supply up to 800mA load current. The
default output voltage ranges from 0.8V to 3.6V depending on the
factory pre-set configuration and can be programmed via the I
2
C
interface in the range of 0.825V to 3.6V at 25mV/step with a
programmable slew rate. An open-drain DCDPG (DCD Power-Good)
signal is also provided to monitor the DCD1 and DCD2 output
voltages. Optionally, both DCD1 and DCD2 can be programmed to
be actively discharged via an on-chip bleeding resistor (typical
115&) when the converter is disabled.
Skip Mode (PFM Mode) for DCD1/DCD2
Under light load condition, the DCD1 and DCD2 can be
programmed to automatically enter a pulse-skipping mode to
minimize the switching loss by reducing the switching frequency.
Figure 2 illustrates the skip mode operation. A zero-cross sensing
circuit monitors the current flowing through the SW node for zero
crossing. When it is detected to cross zero for 16 consecutive
cycles, the regulator enters the skip mode. During the 16
consecutive cycles, the inductor current could be negative. The
counter is reset to zero when the sensed current flowing through
the SW node does not cross zero during any cycle within the 16
consecutive cycles. Once the converter enters the skip mode, the
pulse modulation is controlled by an internal comparator while
each pulse cycle remains synchronized to the PWM clock. The
P-Channel MOSFET is turned on at the rising edge of the clock
and turned off when its current reaches ~20% of the peak
current limit. As the average inductor current in each cycle is
higher than the average current of the load, the output voltage
rises cycle-over-cycle. When the output voltage is sensed to reach
1.5% above its nominal voltage, the P-Channel MOSFET is turned
off immediately and the inductor current is fully discharged to
zero and stays at zero. The output voltage reduces gradually due
to the load current discharging the output capacitor. When the
output voltage drops to the nominal voltage, the P-Channel
MOSFET will be turned on again, repeating the previous
operations.
The regulator resumes normal PWM mode operation when the
output voltage is sensed to drop below 1.5% of its nominal
voltage value as shown in Figure 3.
16 CYCLES
CLOCK
I
L
V
OUT
0
V
OUT_NOMINAL
20% PEAK CURRENT LIMIT
1.015*V
OUT_NOMINAL
FIGURE 2. SKIP MODE OPERATION WAVEFORMS
v
EAMP
 
d
i
L
v
OUT
v
CSA
 
FIGURE 3. PWM OPERATION WAVEFORMS
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