參數(shù)資料
型號(hào): ISL9208
廠商: Intersil Corporation
英文描述: Multi-Cell Li-ion Battery Pack OCP/Analog Front End(多節(jié)鋰離子電池組OCP/模擬前端)
中文描述: 多單元鋰離子電池OCP /模擬前端(多節(jié)鋰離子電池組OCP /模擬前端)
文件頁數(shù): 7/28頁
文件大?。?/td> 504K
代理商: ISL9208
7
FN6446.1
November 2, 2007
ANALOG OUTPUT SPECIFICATIONS
Cell Monitor Analog Output Voltage
Accuracy
V
AOC
[V
CELLN
- (V
CELLN-1
)]/2 - AO
-15
4
30
mV
Cell Monitor Analog Output External
Temperature Accuracy
V
AOXT
External temperature monitoring accuracy.
Voltage error at AO when monitoring
TEMPI voltage (measured with
TEMPI = 1V)
-10
10
mV
Internal Temperature Monitor Output
Voltage Slope
V
INTMON
Internal temperature monitor voltage
change
-3.5
mV/°C
Internal Temperature Monitor Output
T
INT25
Output at +25°C
1.31
V
AO Output Stabilization Time
t
VSC
From SCL falling edge at data bit 0 of
command to AO output stable within 0.5%
of final value. AO voltage steps from 0V to
2V. (C
AO
= 10pF)
(Note 7)
0.1
ms
CELL BALANCE SPECIFICATIONS
Cell Balance Transistor r
DS(ON)
R
CB
(Note 6)
5
Ω
Cell Balance Transistor Current
I
CB
200
mA
WAKE UP/SLEEP SPECIFICATIONS
Device WKUP Pin Voltage Threshold
(WKUP Pin Active High - Rising Edge)
V
WKUP1
WKUP pin rising edge (WKPOL = 1)
Device wakes up and sets WKUP flag
HIGH.
3.5
5.0
6.5
V
Device Wkup Pin Hysteresis
(WKUP Pin Active High)
V
WKUP1H
WKUP pin falling edge hystersis
(WKPOL = 1) sets WKUP flag LOW (does
not automatically enter sleep mode)
100
mV
Input Resistance On WKUP
R
WKUP
Resistance from WKUP pin to VSS
(WKPOL = 1)
130
230
330
k
Ω
Device WKUP Pin Active Voltage
Threshold (WKUP Pin Active Low -
Falling Edge)
V
WKUP2
WKUP pin falling edge (WKPOL = 0)
Device wakes up and sets WKUP flag
HIGH.
V
CELL1
- 2.6
V
CELL1
- 2.0 V
CELL1
- 1.2
V
Device Wkup Pin Hysteresis
(WKUP Pin Active Low)
V
WKUP2H
WKUP pin rising edge hysteresis
(WKPOL = 0) sets WKUP flag LOW (does
not automatically enter sleep mode)
200
mV
Device Wake-up Delay
t
WKUP
Delay after voltage on WKUP pin crosses
the threshold (rising or falling) before
activating the WKUP bit.
20
40
60
ms
FET CONTROL SPECIFICATIONS
(FOR VCELL1, VCELL2, VCELL3 VOLTAGES FROM 2.8V TO 4.3V)
Control Outputs Response Time
(CFET, DFET)
t
CO
Bit 0 to start of control signal (DFET)
Bit 1 to start of control signal (CFET)
1.0
μs
CFET Gate Voltage
VCFET
No load on CFET
V
CELL3
- 0.5
V
CELL3
V
DFETGate Voltage
VDFET
No load on DFET
V
CELL3
- 0.5
V
CELL3
V
FET Turn On Current (DFET)
I
DFON
DFET voltage = 0 to VCELL3 -1.5V
80
130
400
μA
FET Turn On Current (CFET)
I
CF(ON)
CFET voltage = 0 to VCELL3 - 1.5V
80
200
400
μA
FET Turn Off Current (DFET)
I
DF(OFF)
DFET voltage = VDFET to 1V
100
180
mA
DFET Resistance to VSS
R
DF(OFF)
VDFET <1V (When turning off the FET)
11
Ω
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNIT
ISL9208
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