參數(shù)資料
型號： ISL90842WIV1427Z
廠商： INTERSIL CORP
元件分類： 數(shù)字電位計
英文描述： Quad Digitally Controlled Variable Resistors
中文描述： QUAD 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14
封裝： ROHS COMPLIANT, PLASTIC, TSSOP-14
文件頁數(shù)： 4/10頁
文件大?。?/td> 678K
代理商： ISL90842WIV1427Z
4
FN8096.1
January 16, 2006
t
DCP
(Note 8)
DCP wiper response time
SCL falling edge of last bit of DCP data byte
to wiper change
1
μs
SERIAL INTERFACE SPECS
V
IL
A1, A0, SDA, and SCL input buffer
LOW voltage
-0.3
0.3*V
CC
V
V
IH
A1, A0, SDA, and SCL input buffer
HIGH voltage
0.7*V
CC
V
CC
+0.3
V
Hysteresis
(Note 8)
SDA and SCL input buffer hysteresis
0.05*
V
CC
V
V
OL
(Note 8)
SDA output buffer LOW voltage,
sinking 4mA
0
0.4
V
Cpin
(Note 8)
A1, A0, SDA, and SCL pin
capacitance
10
pF
f
SCL
SCL frequency
400
kHz
t
IN
(Note 8)
Pulse width suppression time at SDA
and SCL inputs
Any pulse narrower than the max spec is
suppressed
50
ns
t
AA
(Note 8)
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of V
CC
, until
SDA exits the 30% to 70% of V
CC
window
900
ns
t
BUF
(Note 8)
Time the bus must be free before the
start of a new transmission
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during the following START condition
1300
ns
t
LOW
Clock LOW time
Measured at the 30% of V
CC
crossing
1300
ns
t
HIGH
Clock HIGH time
Measured at the 70% of V
CC
crossing
600
ns
t
SU:STA
START condition setup time
SCL rising edge to SDA falling edge; both
crossing 70% of V
CC
600
ns
t
HD:STA
START condition hold time
From SDA falling edge crossing 30% of V
CC
to SCL falling edge crossing 70% of V
CC
600
ns
t
SU:DAT
Input data setup time
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
100
ns
t
HD:DAT
Input data hold time
From SCL rising edge crossing 70% of V
CC
to SDA entering the 30% to 70% of V
CC
window
0
ns
t
SU:STO
STOP condition hold time
From SCL rising edge crossing 70% of V
CC
,
to SDA rising edge crossing 30% of V
CC
600
ns
t
HD:STO
STOP condition hold time for read, or
volatile only write
From SDA rising edge to SCL falling edge.
Both crossing 70% of V
CC
600
ns
t
DH
(Note 8)
Output data hold time
From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window
0
ns
t
R
(Note 8)
SDA and SCL rise time
From 30% to 70% of V
CC
20 +
0.1 * Cb
250
ns
t
F
(Note 8)
SDA and SCL fall time
From 70% to 30% of V
CC
20 +
0.1 * Cb
250
ns
Cb
(Note 8)
Capacitive loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
(Note 8)
SDA and SCL bus pull-up resistor off-
chip
Maximum is determined by t
R
and t
F
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
1
k
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 1)
MAX
UNIT
ISL90842
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ISL90842WIV1427Z-TK 功能描述:IC POT DGTL QUAD 10K OHM 14TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標準值 35 ppm/°C 存儲器類型:非易失 接口:3 線串口 電源電壓:2.7 V ~ 5.25 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應商設備封裝:8-TDFN-EP（3x3） 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:1399 (CN2011-ZH PDF) 其它名稱:MAX5423ETA+TCT
ISL90843 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digital Controlled Potentiometers (XDCP⑩)
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ISL90843UIU1027Z-TK 功能描述:IC XDCP 256-TAP 50OHM 10-MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 接片:32 電阻（歐姆）:50k 電路數(shù):1 溫度系數(shù):標準值 50 ppm/°C 存儲器類型:易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細型，TSOT-23-6 供應商設備封裝:TSOT-23-6 包裝:帶卷 (TR)
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