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參數(shù)資料
| 型號： | ISL8703IBZT |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | DSP-ADDRESS SEQUENCER, PDSO14 |
| 封裝： | PLASTIC, MS-012AB, SOIC-14 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 351K |
| 代理商： | ISL8703IBZT |
5
FN9250.0
March 14, 2006
sequencing is complete, any subsequently registered UV or OV
event will trigger an immediate and simultaneous reset of all
ENABLE or ENABLE# outputs.
On the ISL8702, ISL8703, ISL8704 and ISL8705, enabling of
on or off sequencing can also be signaled via the SEQ_EN or
SEQ_EN# input pin once voltage compliance is met. Initially the
SEQ_EN pin should be held low and released when sequence
start is desired. The SEQ# is internally pulled high and
sequencing is enabled when it is pulled low. The on sequence
of the ENABLE outputs is as previously described. The off
sequence feature is only available on the variants having the
SEQ_EN or the SEQ_EN# inputs, these being the ISL8702,
ISL8703, ISL8704, ISL8705. The sequence is D off, then C off,
then B off and finally A off. Once SEQ_EN (SEQ_EN#) is
signaled low (high) the TIME cap is charged to 2V once again.
Once this Vth is reached ENABLE_D transitions to its reset
state and CTIM is discharged. A delay and subsequent
sequence off is then determined by TD resistor to ENABLE_C.
Likewise, a delay to ENABLE_B and then ENABLE_A turn-off
is determined by TC and TB resistor values respectively.
With the ISL8700, ISL8701 a quasi down sequencing of the
ENABLE outputs can be achieved by loading the ENABLE pins
with various value capacitors to ground. When a simultaneous
output latch off is invoked, the caps will set the falling ramp of
the various ENABLE outputs thus adjusting the time to Vth for
various DC/DC convertors or other circuitry.
Regardless of IC variant, the FAULT signal is always valid at
operational voltages and can be used as justification for
SEQ_EN release or even controlled with an RC timer for
sequence on.
Programming the Under and Overvoltage Limits
When choosing resistors for the divider remember to keep the
current through the string bounded by power loss at the top end
and noise immunity at the bottom end. For most applications,
total divider resistance in the 10k
-1000k range is advisable
with high precision resistors being used to reduce monitoring
error. Although for the ISL870X two dividers of two resistors
each can be employed to separately monitor the OV and UV
levels for the VIN voltage we will discuss here using a single
three resistor string for monitoring the VIN voltage, referencing
Figure 1. In the three resistor divider string with Ru (upper), Rm
(middle) & Rl (lower) the ratios of each in combination to the
other two is balanced to achieve the desired UV & OV trip
levels. Although this IC has a bias range of 2.5V to 24V (12V for
ISL8702) it can monitor any voltage >1.22V.
The ratio of the desired overvoltage trip point to the internal
reference is equal to the ratio of the two upper resistors to the
lowest (gnd connected) resistor.
The ratio of the desired undervoltage trip point to the internal
reference voltage is equal to the ratio of the uppermost (voltage
connected) resistor to the lower two resistors.
These assumptions are true for both rising (turn-on) or falling
(shutdown) voltages.
The following is a practical example worked out. For detailed
equatons on how to perform this operation for a given supply
requirement please see the next section.
1. Determine if turn-on or shutdown limits are preferred and
in this example we will determine the resistor values
based on the shutdown limits.
2. Establish lower and upper trip level: 12V ±10% or 13.2V
(OV) and 10.8V (UV)
3. Establish total resistor string value: 100k
, Ir = divider
current
4. (Rm+Rl) x Ir = 1.1V @ UV and Rl x Ir = 1.2V @ OV
5. Rm+Rl = 1.1V/Ir @ UV
= Rm+Rl = 1.1V/(10.8V/100k) =
10.370k
6. Rl = 1.2V/Ir @ OV
= Rl = 1.2V/(13.2V/100k) = 9.242k
7. Rm = 10.370k
- 9.242k = 1.128k
8. Ru = 100k
- 10.370k = 89.630k
9. Choose standard value resistors that most closely
approximate these ideal values. Choosing a different total
divider resistance value may yield a more ideal ratio with
available resistors.values.
In our example with the closest standard values of
Ru = 90.9k
, Rm = 1.13k and Rl = 9.31k, the nominal UV
falling and OV rising will be at 10.9V and 13.3V respectively.
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
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| ISL8704AIBZ | 功能描述:監(jiān)控電路 ADJ QD SEQNCR 14N W/ANNEAL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISL8704AIBZ-T | 功能描述:監(jiān)控電路 ADJ QD SEQNCR 14N W/ANNEAL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISL8705AIBZ | 功能描述:監(jiān)控電路 ADJ QD SEQNCR 14N W/ANNEAL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISL8705AIBZ-T | 功能描述:監(jiān)控電路 ADJ QD SEQNCR 14N W/ANNEAL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISL870XEVAL1 | 功能描述:EVAL BOARD 1 FOR ISL870X RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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