Interconnection with 3V and 5V Logic The ISL8563E directly interfaces with 5V CMOS and TTL logic families. Nevertheless, with the device " />
參數(shù)資料
型號: ISL8563ECB
廠商: Intersil
文件頁數(shù): 7/9頁
文件大?。?/td> 0K
描述: XMITTER/RCVR RS562/232 18-SOIC
標準包裝: 40
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 2/2
規(guī)程: RS232,RS562
電源電壓: 3 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 18-SOIC W
包裝: 管件
7
Interconnection with 3V and 5V Logic
The ISL8563E directly interfaces with 5V CMOS and TTL
logic families. Nevertheless, with the device at 3.3V, and the
logic supply at 5V, AC, HC, and CD4000 outputs can drive
ISL83563E inputs, but ISL83563E outputs do not reach the
minimum VIH for these logic families. See Table 3 for more
information.
±15kV ESD Protection
All pins on Intersil 3V interface devices include ESD
protection structures, but the ISL8XXXE family incorporates
advanced structures which allow the RS-562/232 pins
(transmitter outputs and receiver inputs) to survive ESD
events up to
±15kV. These pins are particularly vulnerable to
ESD damage because they typically connect to an exposed
port on the exterior of the finished product. Simply touching
the port pins, or connecting a cable, can cause an ESD event
that might destroy unprotected ICs. These new ESD
structures protect the device whether or not it is powered up,
protect without allowing any latchup mechanism to activate,
and don’t interfere with RS-562/232 signals as large as
±25V.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5k
current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330
limiting resistor. The HBM method
determines an ICs ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-562/232 pins on “E” family
devices can withstand HBM ESD events to
±15kV.
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-562/232 pins in this case), and the IC
is tested in its typical application configuration (power
applied) rather than testing each pin-to-pin combination. The
lower current limiting resistor coupled with the larger charge
FIGURE 7. TRANSMITTER LOOPBACK TEST CIRCUIT
FIGURE 8. LOOPBACK TEST AT 120kbps
FIGURE 9. LOOPBACK TEST AT 250kbps
ISL8563E
VCC
C1
C2
C4
C3
+
1000pF
V+
V-
5K
TIN
ROUT
C1+
C1-
C2+
C2-
RIN
TOUT
+
VCC
0.1
F
VCC
EN
SHDN
400k
VCC
T1IN
T1OUT
R1OUT
5
s/DIV.
VCC = +3.3V
5V/DIV.
C1 - C4 = 0.1
F
T1IN
T1OUT
R1OUT
2
s/DIV
5V/DIV
VCC = +3.3V
C1 - C4 = 0.1
F
TABLE 3. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
VCC
SUPPLY
VOLTAGE
(V)
COMPATIBILITY
3.3
Compatible with all CMOS families.
5
Compatible with all TTL and
CMOS logic families.
5
3.3
Compatible with ACT and HCT
CMOS, and with TTL.
ISL83563E
outputs are incompatible with AC,
HC, and CD4000 CMOS inputs.
ISL8563E
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