4 December 21, 2013 FN7611.2 18 VHSYNCPOL CMOS input for HSYNC and VSYNC Polarity 1: HSYNC & VSYNC active low 0: HSYNC & VSYNC" />
參數(shù)資料
型號(hào)： ISL76322ARZ-TK
廠商： Intersil
文件頁數(shù)： 8/13頁
文件大?。?/td> 0K
描述： IC VIDEO SERDES LONG 16BIT 48QFN
標(biāo)準(zhǔn)包裝： 1,000
功能： 串行器/解串器
輸入類型： RGB
輸出類型： 串行
輸入數(shù)： 16
輸出數(shù)： 1
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-QFN（7x7）
包裝： 帶卷 (TR)
ISL76322
4
December 21, 2013
FN7611.2
18
VHSYNCPOL
CMOS input for HSYNC and VSYNC Polarity
1: HSYNC & VSYNC active low
0: HSYNC & VSYNC active high
19
VIDEO_TX
CMOS input for video flow direction
1: Video serializer
0: Video deserializer
24, 23
SDA, SCL (Note 1)
I2C Interface Pins (I2C DATA, I2C CLK), weak internal pullup
25, 26
I2CA[1:0] (Note 1)
I2C Device Address
27
MASTER
I2C Master Mode
1: Master
0: Slave
12
RSTB/PDB
CMOS input for Reset and Power-down. For normal operation, this pin should be driven high. When this
pin is taken low, the device will be reset. If this pin stays low, the device will be in PD mode.
10
STATUS
CMOS output for Receiver Status:
1: Valid 8b/10b data received
0: No valid data detected
Note: serializer and deserializer switch roles during side-channel reverse traffic
28
REF_RES
Analog bias setting resistor connection; use 3.16k
Ω ±1% to ground
21
GND_P (Note 2)
PLL Ground
37, 48
GND_IO (Note 2)
Digital (Parallel and Control) Ground
35
GND_CDR (Note 2)
Analog (Serial) Data Recovery Ground
31
GND_TX (Note 2)
Analog (Serial) Output Ground
29
GND_AN (Note 2)
Analog Bias Ground
13
GND_CR (Note 2)
Core Logic Ground
14
VDD_CR
Core Logic VDD
34
VDD_TX
Analog (Serial) Output VDD
30
VDD_AN
Analog Bias VDD
36
VDD_CDR
Analog (Serial) Data Recovery VDD
1, 38
VDD_IO (Note 1)
Digital (Parallel and Control) VDD
22
VDD_P
PLL VDD
11
TEST_EN
Must be connected to ground
Exposed Pad
PAD
Must be connected to ground, not an electrical connection
NOTES:
1. Pins with the same name are internally connected together. However, this connection must NOT be used for connecting together external components
or features.
2. The various differently-named Ground pins are internally weakly connected. They must be tied together externally. The different names are provided
to assist in minimizing the current loops involved in bypassing the associated supply VDD pins. In particular, for ESD testing, they should be
considered a common connection.
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
SERIALIZER
DESERIALIZER
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