參數(shù)資料
型號: ISL6413IRZ-TK
廠商: Intersil
文件頁數(shù): 11/12頁
文件大小: 325K
描述: IC REG TRPL BCK/LINEAR 24-QFN
標(biāo)準(zhǔn)包裝: 1,000
拓?fù)洌?/td> 降壓(降壓)同步(1),線性(LDO)(2)
功能: 任何功能
輸出數(shù): 3
頻率 - 開關(guān): 750kHz
電壓/電流 - 輸出 1: 1.8V,400mA
電壓/電流 - 輸出 2: 2.84V,300mA
電壓/電流 - 輸出 3: 2.85V,200mA
帶 LED 驅(qū)動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 帶卷 (TR)
11
In order to avoid saturation of the inductor, the inductor
should be rated at least for the maximum output current plus
the inductor ripple current.
OUTPUT CAPACITOR SELECTION
For best performance, a low ESR output capacitor is
needed. If an output capacitor is selected with an ESR value
d120m&, its RMS ripple current rating will always meet the
application requirements. The RMS ripple current is
calculated as:
The overall output ripple voltage is the sum of the voltage
spike caused by the output capacitor ESR plus the voltage
ripple caused by charge and discharging the output
capacitor:
Where the highest output voltage ripple occurs at the highest
input voltage VI.
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a
pulsating input current, a low ESR input capacitor is required
for best input voltage filtering and minimizing the
interference with other circuits caused by high input voltage
spikes.
The input capacitor should have a minimum value of 10礔
and can be increased without any limit for better input
voltage filtering. The input capacitor should be rated for the
maximum input ripple current calculated as:
The worst case RMS ripple current occurs at D = 0.5.
Ceramic capacitors show good performance because of
their low ESR value, and because they are less sensitive to
voltage transients, compared to tantalum capacitors.
Place the input capacitor as close as possible to the input pin
of the IC for best performance.
Layout Considerations
As for all switching power supplies, the layout is an important
step in the design especially at high peak currents and
switching frequencies. If the layout is not carefully done, the
regulator might show stability problems as well as EMI
problems. Therefore, use wide and short traces for the main
current paths. The input capacitor should be placed as close
as possible to the IC pins as well as the inductor and output
capacitor. Use a common ground node to minimize the
effects of ground noise.
Allocate two board levels as ground planes, with many vias
between them to create a low impedance, high-frequency
plane. Tie all the device ground pins through multiple vias
each to this ground plane, as close to the device as possible.
Also tie the exposed pad on the bottom of the device to this
ground plane.
Refer to application note AN1081.
TABLE 1. RECOMMENDED INDUCTORS
OUTPUT
CURRENT
INDUCTOR
VALUE
VENDOR PART #
COMMENTS
0mA to
600mA
10礖
Coilcraft DO3316P-103
Coilcraft DT3316P-103
Sumida CDR63B-100
Sumida CDRH5D28-100
High
Efficiency
Coilcraft DO1608C-100
Sumida CDRH4D28-100
Smallest
Solution
0mA to
300mA
10礖
Coilcraft DS1608C-103    High
Efficiency
Murata LQH4C100K04    Smallest
Solution
TABLE 2. RECOMMENDED CAPACITORS
CAPACITOR
VALUE
ESR/m&
VENDOR PART #
COMMENTS
10礔
50
Taiyo Yuden
JMK316BJ106KL
Ceramic
47礔
100
Sanyo 6TPA47M
POSCAP
68礔
100
Sprague
594D686X0010C2T
Tantalum
I
RMS C
(  )
O
V
O
1
V
O
V
I
------- -

L   f
?/DIV>
-----------------
1
2
3
?/DIV>
---------------- -
?/DIV>
?/DIV>
=
V
O

V
O
1
V
O
V
I
------- -

L   f
?/DIV>
-----------------
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
1
8   C
O
f
?/DIV>
?/DIV>
------------------------- -   ESR
+
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
I
RMS
I
O max
(
)
V
O
V
I
------- -
1
V
O
V
I
------- -

?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
ISL6413
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