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參數(shù)資料
| 型號(hào)： | ISL6412IR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 固定正電壓多路輸出LDO穩(wěn)壓器 |
| 英文描述： | Hex Inverters 14-SOIC -40 to 85 |
| 中文描述： | TRIPLE OUTPUT, FIXED POSITIVE LDO REGULATOR, PQCC16 |
| 封裝： | 4 X 4 MM, PLASTIC, MO-220VGGC, QFN-16 |
| 文件頁(yè)數(shù)： | 10/10頁(yè) |
| 文件大小： | 199K |
| 代理商： | ISL6412IR |
9
FN9067.1
March 20, 2007
Thermal Overload Protection
Thermal overload protection limits total power dissipation in
the ISL6412. When the junction temperature (TJ) exceeds
+150°C, the thermal sensor sends a signal to the shutdown
logic, turning off the pass transistor and allowing the IC to
cool. The pass transistor turns on again after the IC’s
junction temperature typically cools by 20°C, resulting in a
pulsed output during continuous thermal overload
conditions. Thermal overload protection protects the
ISL6412 against fault conditions. For continuous operation,
do not exceed the absolute maximum junction temperature
rating of +150°C.
Operating Region and Power Dissipation
The maximum power dissipation of ISL6412 depends on the
thermal resistance of the IC package and circuit board, the
temperature difference between the die junction and ambient
air, and the rate of air flow. The power dissipated in the
device is:
PT = P1 + P2 + P3, where
P1 = IOUT1 (VIN – VOUT1)
P2 = IOUT2 (VIN – VOUT2)
P3 = IOUT3 (VIN- VOUT3)
The maximum power dissipation is:
Pmax = (Tjmax – TA)/θJA
Where Tjmax = +150°C, TA = ambient temperature, and θJA
is the thermal resistance from the junction to the surrounding
environment.
The ISL6412 package features an exposed thermal pad on
its underside. This pad lowers the thermal resistance of the
package by providing a direct heat conduction path from the
die to the PC board. Additionally, the ISL6412’s ground
(GND/GND3) performs the dual function of providing an
electrical connection to system ground and channeling heat
away. Connect the exposed backside pad and GND to the
system ground using a large pad or ground plane, or through
multiple vias to the ground plane layer.
Integrator Circuitry
The ISL6412 uses an external 33nF compensation capacitor
for minimizing load and line regulation errors and for
lowering output noise. When the output voltage shifts due to
varying load current or input voltage, the integrator capacitor
voltage is raised or lowered to compensate for the
systematic offset at the error amplifier. Compensation is
limited to ±5% to minimize transient overshoot when the
device goes out of dropout, current limit, or thermal
shutdown.
FAULT Functionality
Applications Information
Capacitor Selection and Regulator Stability
Capacitors are required at the ISL6412’s input and output for
stable operation over the entire load range and the full
temperature range. Use >1F capacitor at the input of
ISL6412. The input capacitor lowers the source impedance
of the input supply. Larger capacitor values and lower ESR
provides better PSRR and line transient response. The input
capacitor must be located at a distance of not more then 0.5
inches from the VIN pins of the IC and returned to a clean
analog ground. Any good quality ceramic or tantalum can be
used as an input capacitor.
The output capacitor must meet the requirements of
minimum amount of capacitance and ESR for all three
LDO’s. The ISL6412 is specifically designed to work with
small ceramic output capacitors. The output capacitor’s ESR
affects stability and output noise. Use an output capacitor
with an ESR of 50m
Ω or less to insure stability and optimum
transient response. For stable operation, a ceramic
capacitor, with a minimum value of 3.3
μF, is recommended
for VOUT1 for 300mA output current, and 2.2μF is
recommended for VOUT2 and VOUT3 each at 200mA load
current. There is no upper limit to the output capacitor value.
Larger capacitor can reduce noise and improve load
transient response, stability and PSRR. Higher value of
output capacitor (10F) is recommended for LDO3 when
used to power VCO circuitry in wireless chipsets. The output
capacitor should be located very close to VOUT pins to
minimize impact of PC board inductances and the other end
of the capacitor should be returned to a clean analog
ground.
Input-Output (Dropout) Voltage
A regulator’s minimum input-output voltage differential (or
dropout voltage) determines the lowest usable supply
voltage. Because the ISL6412 uses a P-channel MOSFET
pass transistor, its dropout voltage is a function of rDS(ON)
(typically 0.5) multiplied by the load current.
TABLE 1.
EVENT
FAULT1
Below UVLO threshold
L
VOUT1 = 1.8V ±8% typ
VOUT2/VOUT3 not in regulation
H
VOUT1 not in regulation
VOUT2 and VOUT3 are in regulation
L
Thermal Shutdown
L
Normal Shutdown with SHDN pin
L
Overcurrent only on LDO1
L
Overcurrent only on LDO2/LDO3
H
ISL6412
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