參數(shù)資料
型號： ISL59424IR-T7
廠商： Intersil
文件頁數(shù)： 13/14頁
文件大小： 0K
描述： IC AMP TRIPLE MUX 1GHZ 24-QFN
標(biāo)準(zhǔn)包裝： 1,000
應(yīng)用： 2:1 多路復(fù)用器-放大器
電路數(shù)： 3
-3db帶寬： 1GHz
轉(zhuǎn)換速率： 1200 V/µs
電流 - 電源： 39mA
電流 - 輸出 / 通道： 130mA
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-QFN（5x4）
包裝： 帶卷 (TR)
8
FN7456.3
September 30, 2011
Pin Descriptions
ISL59445
(32-LD QFN)
ISL59424
(24-LD QFN)
PIN
NAME
EQUIVALENT
CIRCUIT
DESCRIPTION
1
5
IN1A
Circuit 1
Channel 1 input for output amplifier "A"
2, 4, 8, 13, 15,
24, 28, 30
2, 8, 10, 11,
21, 22
NIC
-
Not Internally Connected; it is recommended these pins be tied to ground to
minimize crosstalk.
3
7
IN1B
Circuit 1
Channel 1 input for output amplifier "B"
5
9
IN1C
Circuit 1
Channel 1 input for output amplifier "C"
6
4
GNDB
Circuit 4
Ground pin for output amplifier “B”
7
IN2A
Circuit 1
Channel 2 input for output amplifier "A"
9
IN2B
Circuit 1
Channel 2 input for output amplifier "B"
10
IN2C
Circuit 1
Channel 2 input for output amplifier "C"
11
6
GNDC
Circuit 4
Ground pin for output amplifier “C”
12
IN3A
Circuit 1
Channel 3 input for output amplifier "A"
14
IN3B
Circuit 1
Channel 3 input for output amplifier "B"
16
IN3C
Circuit 1
Channel 3 input for output amplifier "C"
17
S1
Circuit 2
Channel selection pin MSB (binary logic code)
18
13
S0
Circuit 2
Channel selection pin. LSB (binary logic code)
19
14
OUTC
Circuit 3
Output of amplifier “C”
20
16
OUTB
Circuit 3
Output of amplifier “B”
21
15
V-
Circuit 4
Negative power supply
22
18
OUTA
Circuit 3
Output of amplifier “A”
23
17
V+
Circuit 4
Positive power supply
25
19
ENABLE
Circuit 2
Device enable (active low). Internal pull-down resistor ensures the device will be
active with no connection to this pin. A logic High on this pin puts device into
power-down mode. In power-down mode only logic circuitry is active. All logic
states are preserved post power-down. This state is not recommended for logic
control where more than one MUX-amp share the same video output line.
12
LE
Circuit 2
Device latch enable on the ISL59424. A logic high on LE will latch the last (S0, S1)
logic state. HIZ and ENABLE functions are not latched with the LE pin.
26
20
HIZ
Circuit 2
Output disable (active high). Internal pull-down resistor ensures the device will be
active with no connection to this pin. A logic high, puts the outputs in a high
impedance state. Use this state to control logic when more than one MUX-amp
share the same video output line.
27
3
IN0C
Circuit 1
Channel 0 for output amplifier "C"
29
1
IN0B
Circuit 1
Channel 0 for output amplifier "B"
31
23
IN0A
Circuit 1
Channel 0 for output amplifier "A"
32
24
GNDA
Circuit 4
Ground pin for output amplifier “A”
IN
V+
V-
LOGIC PIN
V+
V-
GND
33k
21k
+
-
1.2V
V+
V-
OUT
CIRCUIT 3
CIRCUIT 1
CIRCUIT 2
V-
V+
GND
CAPACITIVELY
COUPLED
ESD CLAMP
GNDC
GNDA
CIRCUIT 4
V-
THERMAL HEAT SINK PAD
~1M
Ω
SUBSTRATE
ISL59424, ISL59445
.
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