參數(shù)資料
型號: ISL55036EVAL1Z
廠商: Intersil
文件頁數(shù): 11/11頁
文件大?。?/td> 0K
描述: EVAL BOARD 1 FOR ISL55036
標準包裝: 1
系列: *
9
FN6640.1
September 11, 2008
Application Information
General
The ISL55036 single supply, fixed gain hex amplifier is well
suited for a variety of video applications. The device features
a PNP ground-sensing input stage and a bipolar rail-to-rail
output stage.
The ISL55036 is designed for general purpose video,
communication, instrumentation, and industrial applications.
The 6 fixed gain amplifiers operate independently, however,
they are organized into 2 triple amplifier groups as shown in
Figure 26. Each group has its own set of power supply pins,
ground pins, enable-disable logic and input ground
reference pins.
Ground Connections
For the best isolation performance and crosstalk rejection,
all GND pins must connect directly to the GND plane. In
addition, the electrically conductive thermal pad should also
connect directly to ground.
Power Considerations
Each triple amplifier group has its own power supply and
ground pins. There are dedicated V+ OUT and GND VOUT
pins to power only the output stage. A separate set of power
and ground pins power the rest of each of the triple op amps
(V+ and PWR GND). Providing separate power pins
provides a way to prevent high speed transient currents in
the output stage from bleeding into the sensitive amplifier
input and gain stages. To maximize crosstalk isolation, each
power supply pin should have its own de-coupling capacitors
connected as close to the pin as possible (0.1F in parallel
with 1nF recommended).
The ESD protection circuits use internal diodes from all pins to
the V+ and ground pins. In addition, a dv/dt-triggered clamp is
connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 on page 2. The dv/dt triggered
clamp imposes a maximum supply turn-on slew rate of 1V/s.
Damaging currents can flow for power supply rates-of-rise in
excess of 1V/s, such as during hot plugging. Under these
conditions, additional methods should be employed to ensure
the maximum rate of rise is not exceeded.
EN and Power-Down States
The EN pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
EN pin. The power-down state is established within
approximately 25ns, if a logic high (>2V) is placed on the EN
pin. In the power-down state, supply current is reduced
significantly by shutting the three amplifiers off. The output
presents a relatively high impedance (~2k
Ω) to the output
pin. Multiplexing several outputs together is possible using
the enable/disable function as long as the application can
tolerate the limited power-down output impedance.
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than 40mA.
Adequate thermal heat sinking of the parts is also required.
PC Board Layout
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
The use of low inductance components, such as chip
resistors and chip capacitors, is strongly recommended.
Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners. Use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
FIGURE 25. PSRR vs TEMPERATURE 4.5V TO 5.5V
Typical Performance Curves (Continued)
80
85
90
95
100
105
110
115
120
PSRR
(dB
)
MEDIAN
MIN
MAX
n = 100
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
ISL55036
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