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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ISL28433FBZ-T7 |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 6/25闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC OPAMP CHOPPR RR .4MHZ 14SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1,000 |
| 鏀惧ぇ鍣ㄩ鍨嬶細 | 鏂疯矾鍣紙闆舵紓绉伙級 |
| 闆昏矾鏁�(sh霉)锛� | 4 |
| 杓稿嚭椤炲瀷锛� | 婊挎摵骞� |
| 杞�(zhu菐n)鎻涢€熺巼锛� | 0.2 V/µs |
| 澧炵泭甯跺绌嶏細 | 400kHz |
| 闆绘祦 - 杓稿叆鍋忓锛� | 180pA |
| 闆诲 - 杓稿叆鍋忕Щ锛� | 2µV |
| 闆绘祦 - 闆绘簮锛� | 18µA |
| 闆绘祦 - 杓稿嚭 / 閫氶亾锛� | 19mA |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | 1.8 V ~ 6 V锛�±0.825 V ~ 3 V |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 14-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 14-SOIC |
| 鍖呰锛� | 甯跺嵎 (TR) |
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ISL28233, ISL28433
14
FN7692.3
July 26, 2011
Applications Information
Functional Description
The ISL28233 and ISL28433 use a proprietary
chopper-stabilized technique (see Figure 39) that combines a
400kHz main amplifier with a very high open loop gain (174dB)
chopper amplifier to achieve very low offset voltage and drift
(2V, 0.01V/掳C typical) while consuming only 18A of supply
current per channel.
This multi-path amplifier architecture contains a time continuous
main amplifier whose input DC offset is corrected by a parallel-
connected, high gain chopper stabilized DC correction amplifier
operating at 100kHz. From DC to ~5kHz, both amplifiers are active
with DC offset correction and most of the low frequency gain is
provided by the chopper amplifier. A 5kHz crossover filter cuts off
the low frequency amplifier path leaving the main amplifier active
out to the 400kHz gain-bandwidth product of the device.
The key benefits of this architecture for precision applications are
very high open loop gain, very low DC offset, and low 1/f noise.
The noise is virtually flat across the frequency range from a few
millihertz out to 100kHz, except for the narrow noise peak at the
amplifier crossover frequency (5kHz).
Rail-to-rail Input and Output (RRIO)
The RRIO CMOS amplifier uses parallel input PMOS and NMOS that
enable the inputs to swing 100mV beyond either supply rail. The
inverting and non-inverting inputs do not have back-to-back input
clamp diodes and are capable of maintaining high input impedance
at high differential input voltages. This is effective in eliminating
output distortion caused by high slew-rate input signals.
The output stage uses common source connected PMOS and
NMOS devices to achieve rail-to-rail output drive capability with
17mA current limit and the capability to swing to within 20mV of
either rail while driving a 10k
惟 load.
IN+ and IN- Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. For applications where
either input is expected to exceed the rails by 0.5V, an external
series resistor must be used to ensure the input currents never
exceed 20mA (see Figure 40).
Layout Guidelines for High Impedance Inputs
To achieve the maximum performance of the high input
impedance and low offset voltage of the ISL28233 and ISL28433
amplifiers, care should be taken in the circuit board layout. The PC
board surface must remain clean and free of moisture to avoid
leakage currents between adjacent traces. Surface coating of the
circuit board will reduce surface moisture and provide a humidity
barrier, reducing parasitic resistance on the board.
High Gain, Precision DC-Coupled Amplifier
The circuit in Figure 41 implements a single-stage DC-coupled
amplifier with an input DC sensitivity of under 100nV that is only
possible using a low VOS amplifier with high open loop gain. High
gain DC amplifiers operating from low voltage supplies are not
practical using typical low offset precision op amps. For example,
a typical precision amplifier in a gain of 10kV/V with a 卤100V
VOS and offset drift 0.5V/掳C of a low offset op amp would
produce a DC error of >1V with an additional 5mV/掳C of
temperature dependent error making it difficult to resolve DC
input voltage changes in the mV range.
The 卤6V max VOS and 0.05V/掳C max temperature drift of the
ISL28233, ISL28433 produces a temperature stable maximum
DC output error of only 卤60mV with a maximum output
temperature drift of 0.5mV/掳C. The additional benefit of a very
low 1/f noise corner frequency and some feedback filtering
enables DC voltages and voltage fluctuations well below 100nV
to be easily detected with a simple single stage amplifier.
ISL28233, ISL28433 SPICE Model
shows the net list for the ISL28233, ISL28433 SPICE model. The
model is a simplified version of the actual device and simulates
important parameters such as noise, Slew Rate, Gain and Phase.
The model uses typical parameters from the 鈥淓lectrical
Specifications Table鈥� on page 5. The poles and zeroes in the
model were determined from the actual open and closed-loop
gain and phase response. This enables the model to present an
accurate AC representation of the actual device. The model is
configured for ambient temperature of +25掳C.
results for the Noise Density, Frequency Response vs Close Loop
Gain, Gain vs Frequency vs CL and Large Signal Step Response (4V).
LICENSE STATEMENT
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as 鈥淟icensee鈥�, a
nonexclusive, nontransferable licence to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
FIGURE 40. INPUT CURRENT LIMITING
-
+
RIN
RL
VIN
VOUT
FIGURE 41. HIGH GAIN, PRECISION DC-COUPLED AMPLIFIER
-
+
100
惟
RL
VIN
VOUT
1M
惟
1M
惟,
100
惟
-2.5V
+2.5V
ACL = 10kV/V
CF
0.018F
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| ISL28433FVZ-T13 | IC OPAMP CHOPPR RR .4MHZ 14TSSOP |
| PCN10C-44S-2.54DSA | DIN CONN RCPT 44 POS 2 ROW STR |
| 81020-560203 | CONN HEADER 20POS R/A LONG T/H |
| EL5205IYZ | IC VFA SLEW DUAL 700MHZ 8-MSOP |
| 81020-550203 | CONN HEADER 20POS R/A SHORT T/H |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ISL28433FBZ-T7A | 鍔熻兘鎻忚堪:IC OPAMP CHOPPR RR .4MHZ 14SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 鏀惧ぇ鍣ㄩ鍨�:闆绘祦妾㈡脯 闆昏矾鏁�(sh霉):1 杓稿嚭椤炲瀷:- 杞�(zhu菐n)鎻涢€熺巼:- 澧炵泭甯跺绌�:125kHz -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:- 闆诲 - 杓稿叆鍋忕Щ:100µV 闆绘祦 - 闆绘簮:1.1µA 闆绘祦 - 杓稿嚭 / 閫氶亾:- 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):- 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:4-WFBGA锛孋SPBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:4-UCSP锛�2x2锛� 鍖呰:鍓垏甯� (CT) 鍏跺畠鍚嶇ū:MAX9634WERS+TCT |
| ISL28433FRTZ | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Dual and Quad Micropower Chopper Stabilized, RRIO Operational Amplifiers |
| ISL28433FRTZ-T13 | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Dual and Quad Micropower Chopper Stabilized, RRIO Operational Amplifiers |
| ISL28433FVZ | 鍔熻兘鎻忚堪:IC OPAMP CHOPPR RR .4MHZ 14TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):2 杓稿嚭椤炲瀷:婊挎摵骞� 杞�(zhu菐n)鎻涢€熺巼:2.1 V/µs 澧炵泭甯跺绌�:3MHz -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:1pA 闆诲 - 杓稿叆鍋忕Щ:2000µV 闆绘祦 - 闆绘簮:750µA 闆绘祦 - 杓稿嚭 / 閫氶亾:16mA 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2.7 V ~ 16 V锛�±1.35 V ~ 8 V 宸ヤ綔婧害:-40°C ~ 125°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:14-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:14-SOIC 鍖呰:鍓垏甯� (CT) 鍏跺畠鍚嶇ū:296-10529-1 |
| ISL28433FVZ-T13 | 鍔熻兘鎻忚堪:IC OPAMP CHOPPR RR .4MHZ 14TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:75 绯诲垪:MicroAmplifier™ 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):1 杓稿嚭椤炲瀷:婊挎摵骞� 杞�(zhu菐n)鎻涢€熺巼:0.03 V/µs 澧炵泭甯跺绌�:100kHz -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:1pA 闆诲 - 杓稿叆鍋忕Щ:60µV 闆绘祦 - 闆绘簮:20µA 闆绘祦 - 杓稿嚭 / 閫氶亾:5mA 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2.3 V ~ 5.5 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-SOIC 鍖呰:绠′欢 |
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