15 FN6728.7 November 15, 2012 Revision History The revision history provided is for informational purposes only an" />
參數(shù)資料
型號(hào): ISL28413FBZ
廠商: Intersil
文件頁(yè)數(shù): 7/23頁(yè)
文件大小: 0K
描述: IC OPAMP GP RRIO 2MHZ QD 14SOIC
標(biāo)準(zhǔn)包裝: 55
放大器類(lèi)型: 通用
電路數(shù): 4
輸出類(lèi)型: 滿(mǎn)擺幅
轉(zhuǎn)換速率: 1 V/µs
增益帶寬積: 2MHz
電流 - 輸入偏壓: 3pA
電壓 - 輸入偏移: 500µV
電流 - 電源: 90µA
電流 - 輸出 / 通道: 22mA
電壓 - 電源,單路/雙路(±): 1.8 V ~ 5.5 V,±0.9 V ~ 2.5 V
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 管件
ISL28113, ISL28213, ISL28413
15
FN6728.7
November 15, 2012
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to Web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
10/25/12
FN6728.7
Ordering Information changes on page 2:
Removed “italics font” on “ISL28213FHZ-T7A” entry
Changed on both the 28213FHZ entries, “Part Marking” from “BCP” to “BEKA”
Added Note 3 Lead Finish Note for 8 Ld SOT-23 package
Added Note 5 reference for all the SOT-23 and SC-70 entries (6 total), after the part marking, and added the note to Table.
Added POD P8.064 on page 23
4/16/12
FN6728.6
Mask changes have been made from RevA to RevB, datasheet updated to reflect new silicon.
Page 4: Vos limits changed from ±5mV to ±4mV at room temp and ±6mV to ±5mV at +125°C.
TcVos, Max spec removed, typical increased from 2 to 5.
Page 7, Replaced Figure 8 with new graph.
Page 7, Replaced Figure 11 with new graph.
Page 8, Replaced Figure 18 with new graph.
5/18/11
FN6728.5
- On page 2, Ordering Information table: ISL28113FHZ-T7 & -T7A PKG DWG # changed from MDP0038 (Obsoleted) to
P5.064A. Removed ISL28213FHZ and added “Coming Soon” to parts ISL28213FHZ-T7A and ISL28413TSSOPEVAL1Z.
- On page 3, Pin Descriptions: Circuit 3 diagram, removed anti-parallel diodes from the IN+ to IN- terminals.
- On page 4, Absolute Maximum Ratings: changed Differential Input Voltage from "0.5V" to "V- - 0.5V to V+ + 0.5V".
- On page 4, updated CMRR and PSRR parameters in Electrical Specifications table with test condition specifiying -40°C
to +125°C typical parameter.
- On page 5, updated Note 6 (“over-temp” note) referenced in MIN and MAX column headings of Electrical Specifications
table from "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested." to new standard "Compliance to datasheet limits is
assured by one or more methods: production test, characterization and/or design."
- On page 9, under “Input ESD Diode Protection,” removed “They also contain back to-back diodes across the input
terminals.” Changed “For applications where the input differential voltage is expected to exceed 0.5V, an external series
resistor...” to “For applications where the input differential voltage may exceed either power supply voltage by 0.5V or
more, an external series resistor...”. Removed “Although the amplifier is fully protected, high input slew rates that exceed
the amplifier slew rate (±1V/s) may cause output distortion.”
- On page 9, Figure 19: updated circuit schematic by removing back-to-back input protection diodes.
- On page 18, replaced Package Outline Drawing MDP0038 (obsolete) with P5.064A.
3/23/10
FN6728.4
Page 1, 2nd paragraph - Added “...SOT23-8 packages...” and changed “SO8” to “SOIC8”.
Also global, changed S08 to SOIC8
Pg 2, Ordering Information table: Part # ISL28213FEZ changed to ISL28213FHZ and Part Marking changed to "TBD"
-Added Related Literature on page 1, updated ordering information by adding Eval boards.
-Added to ordering information part number ISL28213FHZ 8 Ld SOT-23 Package as coming soon.
-Replaced Figure 24 Simulated Input Noise Voltage with following changes:
Y-axis from “10 to 100” to “10,000 to 10”
Removed (A) AC sims.dat (active) from top of graph
Curve changed to improve noise performance
Made changes to Spice Net List as follows:
-Changed Revision from “C” to “D” and added improved noise performance to Revision line.
-Changed in Voltage Noise
“V_V9 29 0 .00035” to “V_V9 29 0 0.45”
“R_R21
28 0 800E3 TC=0,0” to “R_R21
28 0 30”
-Removed TC=0 in Input Stage from R_R1 through C_Cin2
-Removed TC=0 in 1st Gain Stage from R_R9 through R_R12
-Removed TC=0 in 2nd Gain Stage from R_R13 through C_C3
-Changed in Common Mode Gain Stage with Zero
“G_G5
V++ VC VCM VMID 2.5118E-10” to “G_G5
V++ VC VCM VMID 0.25118”
“G_G6
V-- VC VCM VMID 2.5118E-10” to “G_G6
V-- VC VCM VMID 0.25118”
Removed TC=0 from R_R16 through R_R23
-Changed in Pole Stage
“G_G7
V++ 23 VG VMID 188.49e-6” to ‘G_G7
V++ 23 VG VMID 0.18849”
“G_G8
V-- 23 VG VMID 188.49e-6” to “G_G8
V-- 23 VG VMID 0.18849”
Removed TC=0 from R_R17 through C_C5
Removed TC=0 in Output Stage with Correction Current Sources from R_R19 and R_R20
Made changes to Spice Schematic Figure 21 as follows:
-Input Stage - Modified connection to the EOS (voltage control voltage source)
-Added to Thermal Information 8 LD SOT-23 as TBD
-Added to pin configuration for the ISL28213 8 Ld SOT-23
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