9 FN6728.7 November 15, 2012 Applications Information Functional Description The ISL28113, ISL28213 and ISL28413 a" />
參數(shù)資料
型號: ISL28413FBZ
廠商: Intersil
文件頁數(shù): 23/23頁
文件大?。?/td> 0K
描述: IC OPAMP GP RRIO 2MHZ QD 14SOIC
標(biāo)準(zhǔn)包裝: 55
放大器類型: 通用
電路數(shù): 4
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 1 V/µs
增益帶寬積: 2MHz
電流 - 輸入偏壓: 3pA
電壓 - 輸入偏移: 500µV
電流 - 電源: 90µA
電流 - 輸出 / 通道: 22mA
電壓 - 電源,單路/雙路(±): 1.8 V ~ 5.5 V,±0.9 V ~ 2.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 管件
ISL28113, ISL28213, ISL28413
9
FN6728.7
November 15, 2012
Applications Information
Functional Description
The ISL28113, ISL28213 and ISL28413 are single, dual and
quad, CMOS rail-to-rail input, output (RRIO) micropower
operational amplifiers. They are designed to operate from single
supply (1.8V to 5.5V) or dual supply (±0.9V to ±2.75V). The parts
have an input common mode range that extends 100mV above
and below the power supply voltage rails. The output stage can
swing to within 15mV of the supply rails with a 10k load.
Input ESD Diode Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails (see “Pin Descriptions -
Circuit 1” on page 3). For applications where the input voltage
may exceed either power supply voltage by 0.5V or more, an
external series resistor must be used to ensure the input currents
never exceed 20mA (see Figure 19).
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28113, ISL28213 and ISL28413 are immune to
output phase reversal, even when the input voltage is 1V beyond
the supplies.
Unused Channels
If the application requires less than all amplifiers one channel,
the user must configure the unused channel(s) to prevent it from
oscillating. The unused channel(s) will oscillate if the input and
output pins are floating. This will result in higher than expected
supply currents and possible noise injection into the channel
being used. The proper way to prevent this oscillation is to short
the output to the inverting input and ground the positive input (as
shown in Figure 20).
Power Dissipation
It is possible to exceed the +125°C maximum junction
temperatures under certain load, power supply conditions and
ambient temperature conditions. It is therefore important to
calculate the maximum junction temperature (TJMAX) for all
applications to determine if power supply voltages, load
conditions, or package type need to be modified to remain in the
safe operating area. These parameters are related using
Equation 1:
where:
PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
PDMAX for each amplifier can be calculated using Equation 2:
where:
TMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
PDMAX = Maximum power dissipation of 1 amplifier
VS = Total supply voltage
IqMAX = Maximum quiescent supply current of 1 amplifier
VOUTMAX = Maximum output voltage swing of the application
RL = Load resistance
ISL28113, ISL28213 and ISL28413 SPICE
Model
Figure 21 shows the SPICE model schematic and Figure 22 shows
the net list for the SPICE model. The model is a simplified version
of the actual device and simulates important AC and DC
parameters. AC parameters incorporated into the model are: 1/f
and flatband noise, Slew Rate, CMRR, Gain and Phase. The DC
parameters are IOS, total supply current and output voltage swing.
The model uses typical parameters given in the “Electrical
Specifications” Table beginning on page 4. The AVOL is adjusted
for 85dB with the dominate pole at 100Hz. The CMRR is set 72dB,
f = 35kHz). The input stage models the actual device to present an
accurate AC representation. The model is configured for ambient
temperature of +25°C.
Figures 23 through 32 show the characterization vs simulation
results for the Noise Voltage, Closed Loop Gain vs Frequency,
Large Signal 5V Step Response, CMRR and Open Loop Gain
Phase.
FIGURE 19. INPUT ESD DIODE CURRENT LIMITING
-
+
RIN-
RL
VIN-
V+
V-
RIN+
RF
RG
FIGURE 20. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
-
+
T
JMAX
T
MAX
θ
JAxPDMAXTOTAL
+
=
(EQ. 1)
PD
MAX
V
S
I
qMAX
V
S
(
- V
OUTMAX )
V
OUTMAX
R
L
----------------------------
×
+
×
=
(EQ. 2)
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