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參數(shù)資料
| 型號(hào)： | ISL267450AIUZ |
| 廠(chǎng)商： | Intersil |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE |
| 標(biāo)準(zhǔn)包裝： | 980 |
| 系列： | * |
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ISL267440, ISL267450A
11
FN7708.2
June 28, 2012
Functional Description
The ISL267440, ISL267450A are based on a successive
approximation register (SAR) architecture utilizing capacitive
charge redistribution digital to analog converters (DACs).
Figure 21 shows a simplified representation of the converter.
During the acquisition phase (ACQ) the differential input is stored
on the sampling capacitors (CS). The comparator is in a balanced
state since the switch across its inputs is closed. The signal is
fully acquired after tACQ has elapsed, and the switches then
transition to the conversion phase (CONV) so the stored voltage
may be converted to digital format. The comparator will become
unbalanced when the differential switch opens and the input
switches transition (assuming that the stored voltage is not
exactly at mid-scale). The comparator output reflects whether the
stored voltage is above or below mid-scale, which sets the value
of the MSB. The SAR logic then forces the capacitive DACs to
adjust up or down by one quarter of full-scale by switching in
binarily weighted capacitors. Again, the comparator output
reflects whether the stored voltage is above or below the new
value, setting the value of the next lowest bit. This process
repeats until all 12 bits have been resolved.
An external clock must be applied to the SCLOCK pin to generate
a conversion result. The allowable frequency range for SCLOCK is
10kHz to 18MHz (556SPS to 1MSPS). Serial output data is
transmitted on the falling edge of SCLOCK. The receiving device
(FPGA, DSP or Microcontroller) may latch the data on the rising
edge of SCLOCK to maximize set-up and hold times.
A stable, low-noise reference voltage must be applied to the
VREF pin to set the full-scale input range and common-mode
voltage. See “Voltage Reference Input” on page 12 for more
details.
ADC Transfer Function
The output coding for the ISL267440, ISL267450A is twos
complement. The first code transition occurs at successive LSB
values (i.e., 1 LSB, 2 LSB, and so on). The LSB size of the
ISL267450A is 2*VREF/4096, while the LSB size of the
ISL267440 is 2*VREF/1024. The ideal transfer characteristic of
the ISL267440, ISL267450A is shown in Figure 22.
Analog Input
The ISL267440, ISL267450A feature a fully differential input
with a nominal full-scale range equal to twice the applied VREF
voltage. Each input swings VREF VP-P, 180° out of phase from
one another for a total differential input of 2*VREF (refer to
Figure 23). Differential signaling offers several benefits over a
single-ended input, such as:
Doubling of the full-scale input range (and therefore the
dynamic range)
Improved even order harmonic distortion
Better noise immunity due to common mode rejection
Figure 24 shows the relationship between the reference voltage
and the full-scale input range for two different values of VREF.
FIGURE 21. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
VIN
+
VIN
–
VREF
ACQ
CONV
ACQ
CONV
DA
C
D
A
C
SAR
LOGIC
CS
FIGURE 22. IDEAL TRANSFER CHARACTERISTICS
FIGURE 23. DIFFERENTIAL INPUT SIGNALING
1LSB = 2VREF/4096
100...000
100...001
100...010
111...111
000...000
000...001
011...110
011...111
AD
C
CO
DE
ANALOG INPUT
VIN+ – (VIN–)
–VREF
+ LSB
+VREF
– 1LSB
0V
+VREF
– 1LSB
ISL267440,
ISL267450A
VCM
VREF P-P
VIN
+
VIN
–
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL267450AIUZ-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12 BIT 1MSPS SAR ADC 8LD 3 X 3 PROPRIETRY RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ISL267450AIUZ-T7A | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12 BIT 1MSPS SAR ADC 8LD RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ISL267450IBZ | 制造商:Intersil Corporation 功能描述:12 BIT 1MSPS SAR ADC, 8 LD SOIC - Rail/Tube 制造商:Intersil Corporation 功能描述:IC ADC 12BIT SPI/SRL 1MSPS 8SOIC 制造商:Intersil 功能描述:12 Bit 1MSPS SAR ADC , 8 LD SOIC |
| ISL267450IBZ-T | 制造商:Intersil Corporation 功能描述:12 BIT 1MSPS SAR ADC, 8 LD SOIC, T&R - Tape and Reel 制造商:Intersil Corporation 功能描述:IC ADC 12BIT SPI/SRL 1MSPS 8SOIC 制造商:Intersil 功能描述:12 Bit 1MSPS SAR ADC , 8 LD SOIC, T&R |
| ISL267450IBZ-T7A | 制造商:Intersil Corporation 功能描述:12 BIT 1MSPS SAR ADC, 8 LD SOIC, 250PC REEL - Tape and Reel 制造商:Intersil Corporation 功能描述:IC ADC 12BIT SPI/SRL 1M 8-SOIC 制造商:INTERSIL 功能描述:ISL267450 Series 2.7 - 5.25 V 12 Bit 1 MSPS Single Channel ADC - SOIC-8 制造商:Intersil 功能描述:12 Bit 1MSPS SAR ADC , 8 LD SOIC, 250pc R |
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