7 FN7708.2 June 28, 2012 Timing Specifications Limits established by characteriza" />
參數(shù)資料
型號(hào)： ISL267450AIUZ
廠商： Intersil
文件頁(yè)數(shù)： 16/18頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE
標(biāo)準(zhǔn)包裝： 980
系列： *
ISL267440, ISL267450A
7
FN7708.2
June 28, 2012
Timing Specifications Limits established by characterization and are not production tested. VDD = 3.0V to 3.6V, fSCLK =18MHz,
fS =1MSPS, VREF = 2.0V; VDD = 4.75V to 5.25V, fSCLK =18MHz, fS = 1MSPS, VREF =2.5V; VCM = VREF unless otherwise noted. Boldface limits apply over
the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
fSCLK
Clock Frequency
0.01
18
MHz
tSCLK
Clock Period
55
ns
tACQ
Acquisition Time (Note 10)
ns
tCONV
Conversion Time
888
ns
tCSW
CS Pulse Width
10
ns
tCSS
CS Falling Edge to SCLK Falling Edge Setup Time
10
ns
tCDV
CS Falling Edge to SDATA Valid
20
ns
tCLKDV
SCLK Falling Edge to SDATA Valid
40
ns
tSDH
SCLK Falling Edge to SDATA Hold
10
ns
tSW
SCLK Pulse Width
0.4 x tSCLK
0.6 x tSCLK
ns
tDISABLE
SCLK Falling Edge to SDATA Disable Time
(Note 11)
Extrapolated back to true bus relinquish
10
35
ns
tQUIET
Quiet Time Before Sample
60
ns
NOTE:
10. Read the “Acquisition Time” section on page 13 for a discussion of this parameter.
11. During characterization, tDISABLE is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the
AD7440/450A loading (25pF) is calculated.
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
FIGURE 4. EQUIVALENT LOAD CIRCUIT
OUTPUT
PIN
CL
10pF
VDD
2.85k
Ω
RL
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