14 FN8273.1 September 5, 2013 Input Multiplexer The input of the multiplex" />
參數(shù)資料
型號(hào)： ISL26329FVZ
廠商： Intersil
文件頁(yè)數(shù)： 6/23頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT SPI/SRL 16-TSSOP
標(biāo)準(zhǔn)包裝： 960
位數(shù)： 12
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 80mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
輸入數(shù)目和類型： 8 個(gè)單端，單極
ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329
14
FN8273.1
September 5, 2013
Input Multiplexer
The input of the multiplexer connects the selected analog input
pins to the ADC input. A proprietary sampling circuit significantly
reduces the input drive requirements, resulting in lower overall
cost and board space in addition to improved performance. Note
that the input capacitance is only 2-3pF during the Sampling
phase, changing to 40pF during the Settling phase, resulting in
an average input current of 2.5A and an effective input
capacitance of only 4pF (see Figure 26).
Voltage Reference Input
An external reference voltage must be supplied to theVREF pin to set
the full-scale input range of the converter. The VREF input on these
devices can accept voltages ranging from 2V (nominal) to VDD,
however, they are specified with VREF at a voltage of 5V with VDD at
5V. Note that exceeding VDD by more than 100mV can forward bias
the ESD protection diodes and degrade measurement accuracy due
to leakage current. A lower value voltage reference must be used if
the device is operated with VDD at voltages lower than 5V. If the
VREF pin is tied to the VDD pin, the VREF pin should be decoupled
with a local 1F ceramic capacitor as described in a later paragraph.
Figures 27 and 28 illustrate possible voltage reference options
for these ADCs. Figure 27 uses the precision ISL21090 voltage
reference, which exhibits exceptionally low drift and low noise.
The ISL21090 must be powered from a supply greater than 4.7V.
Figure 28 illustrates the ISL21010 voltage reference used with
these ADCs. The ISL21010 series voltage references have higher
noise and drift than the ISL21090 devices, but operate at lower
supply voltages. Therefore, these devices can readily be used
when these SAR ADCs operate with VDD at voltages less than 5V.
The outputs of ISL21090 or the ISL21010 devices should be
decoupled with a 1F ceramic capacitor. A 1F, 6.3 V, X7R, 0603
(1608 metric) MLCC type capacitor is recommended for its high
frequency performance. The trace length from the VREF pin to
this capacitor and the voltage reference output should be as
short as possible.
The ISL26320 and ISL26323 devices (packaged in 8 pin SOIC
packages) derive their voltage reference from the VDD pin. To
achieve best performance, the VDD pin of these devices should
be bypassed with the 1F ceramic capacitor mentioned above.
Power-Down/Standby Modes
In order to reduce power consumption between conversions, a
number of user-selectable modes can be utilized by setting the
appropriate bits in the Configuration Register.
Auto Power-down (PD0 = 0) reduces power consumption by
shutting down all portions of the device except the oscillator and
digital interface after completion of a conversion. There is a short
recovery period after CNV is asserted Low (150s with external
reference).
In Auto Sleep mode (PD1 = 1), the device will automatically enter
the low-power Sleep mode at the end of the current conversion.
Recovery from this mode involves only 2.1s and may offer an
alternative to Power-down mode in some applications.
Output Data Format
The converter output word is delivered in two’s complement
format in differential input mode, and straight binary in
single-ended input mode of operation respectively, all MSB-first.
Input exceeding the specified full-scale voltage results in a clipped
output which will not return to in-range values until after the input
signal has returned to the specified allowable voltage range.
Data must be read prior to the completion of the current
conversion to avoid conflict and loss of data, due to overwriting of
the new conversion data into the output register.
FIGURE 25. RELATIONSHIP BETWEEN VREF AND FULL-SCALE
RANGE FOR SINGLE-ENDED INPUTS
3.0
5.0
2.0
1.0
4.0
AIN
2.5Vp-p
VREF = 2.5V
3.0
5.0
2.0
1.0
4.0
AIN
5Vp-p
VREF = 5V
t
V
t
V
FIGURE 26. INPUT SAMPLING OPERATION
INPUT VOLTAGE
OFFSET ERROR
AC
ERROR
TOTAL
ERROR
DC
ERROR
SETTLING ERROR AND NOISE
SAMPLING PHASE
ETTING PHASE
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ISL26329FVZ-T7A 功能描述:IC ADC 12BIT SPI/SRL 8CH 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):10 采樣率（每秒）:357k 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:830µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:10-TDFN-EP（3x3） 包裝:剪切帶 (CT) 輸入數(shù)目和類型:2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極 產(chǎn)品目錄頁(yè)面:1396 (CN2011-ZH PDF) 其它名稱:MAX1395ETB+TCT
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