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參數資料
| 型號： | ISL23325UFVZ |
| 廠商： | Intersil |
| 文件頁數： | 19/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 256POS 50K 14TSSOP |
| 標準包裝： | 960 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數： | 2 |
| 溫度系數： | 標準值 65 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 1.2 V ~ 5.5 V，1.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設備封裝： | * |
| 包裝： | * |
ISL23325
8
FN7870.0
June 21, 2011
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing
70% of VLOGIC to SDA entering
the 30% to 70% of VLOGIC
window
0ns
tSU:STO
STOP Condition Set-up Time
From SCL rising edge crossing
70% of VLOGIC, to SDA rising
edge crossing 30% of VLOGIC
600
ns
tHD:STO
STOP Condition Hold Time for Read
or Write
From SDA rising edge to SCL
falling edge; both crossing
70% of VLOGIC
1300
ns
tDH
Output Data Hold Time
From SCL falling edge crossing
30% of VLOGIC, until SDA
enters the 30% to 70% of
VLOGIC window.
IOL =3mA, VLOGIC > 2V.
IOL = 0.5mA, VLOGIC < 2V
0ns
tR
SDA and SCL Rise Time
From 30% to 70% of VLOGIC
20 + 0.1 x Cb
250
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VLOGIC
20 + 0.1 x Cb
250
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
tSU:A
A2, A1, A0 Setup Time
Before START condition
600
ns
tHD:A
A2, A1, A0 Hold Time
After STOP condition
600
ns
NOTES:
8. Typical values are for TA = +25°C and 3.3V supply voltages.
9. LSB = [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental
voltage when changing from one tap to an adjacent tap.
10. ZS error = V(RW)0/LSB.
11. FS error = [V(RW)255 – VCC]/LSB.
12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
13. INL = [V(RW)i – i LSB – V(RW)0]/LSB for i = 1 to 255
14.
For i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage
and Min( ) is the minimum value of the wiper voltage over the temperature range.
15. MI =
|RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00
hex respectively.
16. Roffset = RW0/MI, when measuring between RW and RL.
Roffset = RW255/MI, when measuring between RW and RH.
17. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 255.
18. RINL = [RWi – (MI i) – RW0]/MI, for i = 16 to 255.
19.
for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC
first followed by the VCC.
22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 255, x = 0 to 1 and y = 0 to 1.
23. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 255 , x = 0 to 1 and y = 0 to 1.
Serial Interface Specification For SCL, SDA, A0, A1, A2 unless otherwise noted. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
UNITS
TCV
Max V RW
()i
() Min V RW
()i
()
–
VRWi +25°C
()
------------------------------------------------------------------------------
106
+165°C
---------------------
×
=
TCR
Max Ri
() Min Ri
()
–
[]
Ri +25°C
()
-------------------------------------------------------
10
6
+165°C
---------------------
×
=
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