- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2001 > ISL1219IUZ-T (Intersil)IC RTC LP BATT BACK SRAM 10MSOP PDF資料下載
參數(shù)資料
| 型號： | ISL1219IUZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC LP BATT BACK SRAM 10MSOP |
| 產(chǎn)品培訓模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 2,500 |
| 類型： | 時間事件記錄器 |
| 特點： | 警報器，閏年，SRAM |
| 存儲容量： | 2B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
14
FN6314.2
July 15, 2010
AUTO RESET ENABLE BIT (ARST)
This bit enables/disables the automatic reset of the BAT and
ALM, EVT status bits only. When ARST bit is set to “1”, these
status bits are reset to “0” after a valid read of the Status
Register (with a valid STOP condition). When the ARST is
cleared to “0”, the user must manually reset the BAT, ALM,
and EVT bits.
INTERRUPT CONTROL REGISTER (INT)
The interrupt control register contains Frequency Output,
Alarm, and Battery switchover control bits.
NOTE: Writing to register 08h has restrictions. If VBAT>VDD, then no
byte writes to register 08h are allowed, only page writes beginning
with register 07h. If VDD>VBAT, then a byte write to register 08h IS
allowed, as well as page writes.
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
select the output frequency at the IRQ/FOUT pin. See
Table 8 for frequency selection. When the frequency mode is
enabled, it will override the alarm mode at the IRQ/FOUT pin.
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the FOUT/IRQ pin during battery
backup mode (i.e. VBAT power source active). When the
FOBATB is set to “1” the FOUT/IRQ pin is disabled during
battery backup mode. This means that both the frequency
output and alarm output functions are disabled. When the
FOBATB is cleared to “0”, the FOUT/IRQ pin is enabled
during battery backup mode.
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
VBAT supply will be used when VDD < VBAT - VBATHYS and
VDD < VTRIP. With LPMODE = “1”, the device will be in low
power mode and the VBAT supply will be used when
VDD < VBAT -VBATHYS. There is a supply current saving of
about 600nA when using LPMODE = “1” with VDD = 5V. (see
Typical Performance Curves: IDD vs VDD with LPMODE ON
& OFF on page 6).
It should be noted that any writes to the LPMODE bit that
may put the device into Low Power Mode should be avoided
if VDD<VBAT, as the device will no longer communicate over
the I2C interface (until VDD rises above VBAT).
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
is cleared to “0”, the alarm function is disabled. The alarm
function can operate in either a single event alarm or a periodic
interrupt alarm (see IM bit).
NOTE: When the frequency output mode is enabled, the alarm function
is disabled.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ/FOUT pin when the RTC is
triggered by the alarm as defined by the alarm registers (0Ch
to 11h). When the IM bit is cleared to “0”, the alarm will
operate in standard mode, where the IRQ/FOUT pin will be
tied low until the ALM status bit is cleared to “0”.
EVENT DETECTION REGISTER (EV)
The ISL1219 provides an easy to use event and tamper
detection circuit. The Event Detection Register configures
the functionality of the event detection circuits.
EVENT INPUT SAMPLING SELECTION BITS
(ESMP<1:0>)
These two bits select the rate of sampling of the EVIN pin to
trigger an event detection. For example, a 2Hz sampling rate
would configure the ISL1219 to check the status of the EV
TABLE 7. INTERRUPT CONTROL REGISTER (INT)
ADDR
7
6
5
4
3210
08h
IM ALME LPMODE FOBATB FO3 FO2 FO1 FO0
Default
0
0000
TABLE 8. FREQUENCY SELECTION OF FOUT PIN
FREQUENCY,
FOUT
UNITS
FO3
FO2
FO1
FO0
0
Hz
0
000
32768
Hz
0
1
4096
Hz
0
1
0
1024
Hz
0
1
64
Hz
0
100
32
Hz
0
101
16
Hz
0
110
8
Hz
0
111
4
Hz
1
000
2
Hz
1
001
1
Hz
1
010
1/2
Hz
1
011
1/4
Hz
1
100
1/8
Hz
1
101
1/16
Hz
1
110
1/32
Hz
1
111
TABLE 9.
IM BIT
INTERRUPT/ALARM FREQUENCY
0
Single Time Event Set By Alarm
1
Repetitive/Recurring Time Event Set By Alarm
ISL1219
相關PDF資料 |
PDF描述 |
|---|---|
| ISL1220IUZ | IC RTC LP BATT BACK SRAM 10MSOP |
| ISL1221IUZ | IC RTC LP BATT BACK SRAM 10MSOP |
| ISL26134AVZ | IC ADC 24BIT SRL 80SPS 28TSSOP |
| ISL26319FVZ-T7A | IC ADC 12BIT SRL/SPI 16TSSOP |
| ISL26329FVZ | IC ADC 12BIT SPI/SRL 16-TSSOP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISL1220 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:I2C㈢ Real Time Clock/Calendar with Frequency Output |
| ISL1220IUZ | 功能描述:實時時鐘 REAL TIME CLKRTC IN RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL1220IUZ-T | 功能描述:實時時鐘 REAL TIME CLKRTC IN RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL1221 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed |
| ISL1221IUZ | 功能描述:實時時鐘 REAL TIME CLKRTC IN RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。