參數(shù)資料
型號(hào): ISL12025IVZ
廠商: Intersil
文件頁(yè)數(shù): 9/27頁(yè)
文件大?。?/td> 0K
描述: IC RTC/CALENDAR EEPROM 8-TSSOP
標(biāo)準(zhǔn)包裝: 960
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,監(jiān)控器,唯一 ID,監(jiān)視計(jì)時(shí)器
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 管件
17
FN6371.3
August 13, 2008
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The first 4-bits of the Slave Address Byte
specify access to either the EEPROM array or to the CCR.
Slave bits ‘1010’ access the EEPROM array. Slave bits
‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the customer
to a known state.
Bit 3 through Bit 1 of the slave byte specify the device select
bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the operation
to be performed. When this R/W bit is a one, then a read
SCL
SDA
START
STOP
FIGURE 17. VALID START AND STOP CONDITIONS
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
8
1
9
START
ACKNOWLEDGE
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
SLAVE ADDRESS BYTE
BYTE 0
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
DATA BYTE
BYTE 3
A6
A5
00
0
A8
0
1
0
1
0
1
0
1
R/W
1
DEVICE IDENTIFIER
ARRAY
CCR
0
WORD ADDRESS 1
BYTE 1
WORD ADDRESS 0
BYTE 2
FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (64 BYTE PAGES)
ISL12025
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