tLOW Clock LOW Time Measured at the 30% of V
參數(shù)資料
型號(hào): ISL12025IVZ
廠商: Intersil
文件頁(yè)數(shù): 23/27頁(yè)
文件大小: 0K
描述: IC RTC/CALENDAR EEPROM 8-TSSOP
標(biāo)準(zhǔn)包裝: 960
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,監(jiān)控器,唯一 ID,監(jiān)視計(jì)時(shí)器
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 管件
5
FN6371.3
August 13, 2008
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA falling
edge. Both crossing 70% of VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD.
600
ns
tSU:DAT
Input Data Set-up Time
From SDA exiting the 30% to 70%
of VDD window, to SCL rising edge
crossing 30% of VDD.
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing
70% of VDD to SDA entering the
30% to 70% of VDD window.
0ns
tSU:STO
STOP Condition Set-up Time
From SCL rising edge crossing
70% of VDD, to SDA rising edge
crossing 30% of VDD.
600
ns
tHD:STO STOP Condition Hold Time for
Read or Volatile Only Write
From SDA rising edge to SCL
falling edge. Both crossing 70% of
VDD.
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing
30% of VDD, until SDA enters the
30% to 70% of VDD window.
0ns
Cpin
SDA and SCL Pin Capacitance
10
pF
tWC
Non-Volatile Write Cycle Time
12
20
ms
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 +
0.1xCb
250
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1xCb
250
ns
Cb
Capacitive loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
RPU
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by tR and
tF.
For Cb = 400pF, max is about
2k
Ω~2.5kΩ.
For Cb = 40pF, max is about
15k
Ω~20kΩ
1k
Ω
NOTES:
3. RESET Inactive (no reset).
4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz.
5. VRESET = 2.63V (VDD must be greater than VRESET), VBAT = 0V.
6. Bit BSW = 0 (Standard Mode), ATR=00h, VBAT ≥1.8V.
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
9. Parameter is not 100% tested.
10. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.
11. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Serial Interface (I2C) Specifications (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 12)
TYP
MAX
(Note 12)
UNITS
NOTES
ISL12025
相關(guān)PDF資料
PDF描述
ISL12026IBZ-T7A IC RTC/CALENDAR EEPROM 8SOIC
ISL12027IV27AZ IC RTC/CALENDAR EEPROM 8-TSSOP
ISL12028IVZ IC RTC/CALENDAR EEPROM 14-TSSOP
ISL12029IVZ IC RTC/CALENDAR EEPROM 14-TSSOP
ISL12030IBZ IC RTC/CALENDAR EEPROM 8-SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISL12025IVZ-T 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK/CLNDR W/EEPROM 2 63SET 8 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
ISL12026 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock/Calendar with I2C Bus? and EEPROM
ISL12026_08 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock/Calendar with I2C Bus? and EEPROM
ISL12026_10 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock/Calendar with I2C Bus? and EEPROM
ISL12026A 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock/Calendar with I2C Bus? and EEPROM