參數(shù)資料
型號(hào): IS93C66-3GI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 4,096-BIT SERIAL ELECTRICALLY ERASABLE PROM
中文描述: 256 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8
封裝: SO-8
文件頁(yè)數(shù): 3/10頁(yè)
文件大?。?/td> 83K
代理商: IS93C66-3GI
Integrated Silicon Solution, Inc.
1-800-379-4774
Rev. G
04/26/01
3
IS93C66-3
ISSI
As with the WRITE instruction, if CS is brought HIGH after
a minimum wait of 250 ns (t
CS
), the D
OUT
pin indicates the
READY/
BUSY
status of the chip (see Figure 6).
W
rite Disable (WDS)
The write disable (WDS) instruction disables all
programming capabilities. This protects the entire part
against accidental modification of data until a WEN
instruction is executed. (When Vcc is applied, this part
powers up in the write disabled state.) To protect data, a
WDS instruction should be executed upon completion of
each programming operation. (NOTE: Neither the WEN
nor the WDS instruction has any effect on the READ
instruction.) (See Figure 7.)
Erase Register (ERASE)
After the erase instruction is entered, CS must be brought
LOW. The falling edge of CS initiates the self-timed
internal programming cycle. Bringing CS HIGH after a
minimum of t
CS
, will cause D
OUT
to indicate the
READ/
BUSY
status of the chip: a logical
0
indicates programming is
still in progress; a logical
1
indicates the erase cycle is
complete and the part is ready for another instruction (see
Figure 8).
Erase All (ERAL)
Full chip erase is provided for ease of programming.
Erasing the entire chip involves setting all bits in the entire
memory array to a logical
1
(see Figure 9).
remains in a write disabled state until a WEN instruction
is executed. Thereafter, the device remains enabled until
a WDS instruction is executed or until Vcc is removed.
(NOTE: Neither the WEN nor the WDS instruction has any
effect on the READ instruction.) (See Figure 4.)
Write (WRITE)
The WRITE instruction includes 16 bits of data to be
written into the specified register. After the last data bit
has been applied to D
IN
, and before the next rising edge of
SK, CS must be brought LOW. The falling edge of CS
initiates the self-timed programming cycle.
After a minimum wait of 250 ns (5V operation) from the
falling edge of CS (t
CS
), if CS is brought HIGH, D
OUT
will
indicate the READY/
BUSY
status of the chip: logical
0
means programming is still in progress; logical
1
means
the selected register has been written, and the part is
ready for another instruction (see Figure 5). (NOTE: The
combination of CS HIGH, D
IN
HIGH and the rising edge of
the SK clock, resets the READY/
BUSY
flag. Therefore, it
is important if you want to access the READY/
BUSY
flag
not to reset it through this combination of control signals.)
Before a WRITE instruction can be executed, the device
must be write enabled (see WEN).
Write All (WRALL)
The write all (WRALL) instruction programs all registers
with the data pattern specified in the instruction. While the
WRALL instruction is being loaded, the address field
becomes a sequence of
Don
t Care
bits (see Figure 6).
INSTRUCTION SET
Instruction
Start Bit
OP Code
Address
Input Data
READ
1
10
(A7-A0)
WEN
(Write Enable)
1
00
11XXXXXX
WRITE
1
01
(A7-A0)
D15-D0
(1)
WRALL
1
00
01XXXXXX
D15-D0
(1)
(Write All Registers)
WDS
(Write Disable)
1
00
00XXXXXX
ERASE
1
11
(A7-A0)
ERAL
(Erase All Registers)
1
00
10XXXXXX
Note:
1. If input data is not 16 bits exactly, the last 16 bits will be taken as input data (a word).
相關(guān)PDF資料
PDF描述
IS93C66-3GR 4,096-BIT SERIAL ELECTRICALLY ERASABLE PROM
IS93C66-3GRI 4,096-BIT SERIAL ELECTRICALLY ERASABLE PROM
IS93C66-3P 4,096-BIT SERIAL ELECTRICALLY ERASABLE PROM
IS93C66-3PI 4,096-BIT SERIAL ELECTRICALLY ERASABLE PROM
IS93C66-3 4,096-Bit Serial EEPROM(4KB串行EEPROM)
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IS93C66-3GR 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:4,096-BIT SERIAL ELECTRICALLY ERASABLE PROM
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IS93C66-3PI 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:4,096-BIT SERIAL ELECTRICALLY ERASABLE PROM
IS93C66A 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM