參數(shù)資料
      型號(hào): IS80LV52-40W
      廠商: INTEGRATED SILICON SOLUTION INC
      元件分類: 微控制器/微處理器
      英文描述: CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER
      中文描述: 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PDIP40
      封裝: 0.600 INCH, PLASTIC, DIP-40
      文件頁數(shù): 34/48頁
      文件大?。?/td> 408K
      代理商: IS80LV52-40W
      IS80LV52
      IS80LV32
      34
      Integrated Silicon Solution, Inc. — 1-800-379-4774
      ADVANCE INFORMATION
      MC019-0A
      10/01/98
      ISSI
      Power-on Reset
      An automatic reset can be obtained when V
      CC
      goes
      through a 10
      μ
      F capacitor and GND through an 8.2K
      resistor, providing the V
      CC
      rise time does not exceed
      1 msec
      and the oscillator start-up time does not exceed
      10 msec. This power-on reset circuit is shown in Figure
      21. The CMOS devices do not require the 8.2K pulldown
      resistor, although its presence does no harm.
      When power is turned on, the circuit holds the RST pin
      high for an amount of time that depends on the value of the
      capacitor and the rate at which it charges. To ensure a
      good reset, the RST pin must be high long enough to allow
      the oscillator time to start-up (normally a few msec) plus
      two machine cycles.
      Note that the port pins will be in a random state until the
      oscillator has start and the internal reset algorithm has
      written 1s to them.
      With this circuit, reducing V
      CC
      quickly to 0 causes the RST
      pin voltage to momentarily fall below 0V. However, this
      voltage is internally limited, and will not harm the device.
      Figure 21. Power-On Reset Circuit
      Vcc
      RST
      GND
      Vcc
      IS80LV52/32
      10 f
      8.2K
      +
      Figure 22. Reset Timing
      12 OSC. PERIODS
      ALE
      RST
      SAMPLE
      RST
      SAMPLE
      RST
      INTERNAL RESET SIGNAL
      PSEN
      P0
      11 OSC. PERIODS
      INST
      ADDR
      INST
      INST
      INST
      19 OSC. PERIODS
      S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4
      ADDR
      ADDR
      ADDR
      INST
      ADDR
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