參數(shù)資料
型號(hào): IS75V16F128GS32-7065BI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: 存儲(chǔ)器
英文描述: 3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA107
封裝: 9 X 10 MM, 0.80 MM PITCH, FBGA-107
文件頁數(shù): 38/52頁
文件大?。?/td> 264K
代理商: IS75V16F128GS32-7065BI
38
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00D
03/24/03
IS75V16F128GS32
ISSI
PSRAM READ OPERATIONS
Parameter
Symbol
Min
Max.
Unit
Read Cycle Time
Chip Enable Access Time
(1,3)
Output Enable Access Time
(1)
Address Access Time
(1,4)
Output Data Hold Time
(1)
CE
1r Low to Output Low-Z
(2)
OE
Low to Output Low-Z
(2)
CE
1r High to Output High-Z
(2)
OE
High to Output High-Z
(2)
Address Setup Time to
CE
1r Low
(5)
Address Setup Time to
OE
(3,6)
Address Setup Time to
OE
(7)
LB/UB
Set up Time to
CE
1r Low
(5)
t
RC
70
ns
t
CE
65
ns
t
OE
40
ns
t
AA
65
ns
t
OH
5
ns
t
CLZ
5
ns
t
OLZ
0
ns
t
CHZ
20
ns
t
OHZ
20
ns
t
ASC
-5
ns
t
ASO
25
ns
t
ASO
(
ABS
)
10
ns
t
BSC
-5
ns
LB/UB
Set up Time to
OE
Low
Address Invalid Time
(4)
Address Hold Time
from
CE
1r Low
(4)
Address Hold Time
from
OE
Low
(4,8)
t
BSO
-10
ns
t
AX
5
ns
t
CLAH
70
ns
t
OLAH
45
ns
Address Hold Time from
CE
1r High
t
CHAH
-5
ns
Address Hold Time from
OE
High
t
OHAH
-5
ns
LB/UB
Hold Time to
CE
1r Low
t
CHBH
-5
ns
LB/UB
Hold Time to
OE
Low
CE
1r Low to
OE
Low Delay Time
(3,6,8,9)
OE
Low to
CE
1r High Delay Time
(8)
t
OHBH
-5
ns
t
CLOL
25
1000
ns
t
OLCH
45
ns
CE
1r High Pulse Width
OE
High Pulse Width
(6,8,9)
OE
High Pulse Width
(7)
Notes:
1. The output load is 30 pF.
2. The output load is 5 pF.
3. The t
CE
is applicable if
OE
is brought to Low before
CE
1r goes Low and is also applicable if actual value of both
or either t
ASO
or t
CLOL
is shorter than specified value.
4. Applicable only to A0 and A1 when both
CE
1r and
OE
are kept at Low for the address access.
5. Applicable if
OE
is brought to Low before
CE
1r goes Low.
6. The t
ASO
, t
CLOL
(Min) and
t
OP
(Min) are reference values when the access time is determined by t
OE
.
If the actual value of each parameter is shorter than the specified minimum value, t
OE
becomes longer by the amount
of subtracting actual value from specified minimum value.
For example, if actual t
ASO
, t
ASO
(actual) , is shorter than specified minimum value, t
ASO
(Min) , during
OE
control
access (i.e.,
CE
1r stays Low) , the t
OE
becomes t
OE
(Max) + t
ASO
(Min) - t
ASO
(actual) .
7. The t
ASO
[
ABS
] and t
OP
[
ABS
] are the absolute minimum values during
OE
control access.
8. If actual value of either t
CLOL
or t
OP
is shorter than specified minimum value, both t
OLAH
and t
OLCH
become t
RC
(Min)
- t
CLOL
(actual) or t
RC
(Min) - t
OP
(actual) .
9. Maximum value is applicable if
CE
1r is kept at Low
.
t
CP
12
ns
t
OP
25
1000
ns
t
OP
(
ABS
)
12
ns
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