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參數(shù)資料
| 型號(hào)： | IS62WV25616BLL-70T |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 70 ns, PDSO44 |
| 封裝： | PLASTIC, TSOP2-44 |
| 文件頁(yè)數(shù)： | 9/14頁(yè) |
| 文件大?。?/td> | 115K |
| 代理商： | IS62WV25616BLL-70T |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)
IS62WV25616ALL, IS62WV25616BLL
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
05/02/05
9
WRITE CYCLE NO. 2
(
WE
Controlled:
OE
is HIGH During Write Cycle)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
WE
LB
,
UB
DOUT
DIN
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the
CS1
and
WE
inputs and at
least one of the
LB
and
UB
inputs being in the LOW state.
2. WRITE = (
CS1
) [ (
LB
) = (
UB
) ] (
WE
).
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(
CS1
Controlled,
OE
= HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
WE
DOUT
DIN
LB
,
UB
t
PWB
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS62WV25616CLL-70BI | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS62WV25616DALL/DBLL | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
| IS62WV25616DALL-55BI | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
| IS62WV25616DALL-55BLI | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
| IS62WV25616DALL-55TI | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
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