參數(shù)資料
型號(hào): IS62VV25616LL-85M
英文描述: x16 SRAM
中文描述: x16的SRAM
文件頁(yè)數(shù): 7/10頁(yè)
文件大?。?/td> 88K
代理商: IS62VV25616LL-85M
Integrated Silicon Solution, Inc.
1-800-379-4774
Rev. A
11/01/01
7
IS62VV25616LL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-70
-85
Symbol
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWB
t
PWE
t
SD
t
HD
t
HZWE
(3)
t
LZWE
(3)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and
output loading specified in Figure 1.
2.
The internal write time is defined by the overlap of
CE
LOW and
UB
or
LB
, and
WE
LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Parameter
Write Cycle Time
CE
to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
LB
,
UB
Valid to End of Write
WE
Pulse Width
Data Setup to Write End
Data Hold from Write End
WE
LOW to High-Z Output
Min.
70
65
65
0
0
60
55
30
0
Max.
30
Min.
85
70
70
0
0
70
60
35
0
Max.
30
Unit
1ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WE
HIGH to Low-Z Output
5
5
ns
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the
CE
and
WE
inputs and at least one of
the
LB
and
UB
inputs being in the LOW state.
2. WRITE = (
CE
) [ (
LB
) = (
UB
) ] (
WE
).
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(
CE
Controlled,
OE
= HIGH or LOW)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCS
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB
,
LB
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
UB_CSWR1.eps
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