參數(shù)資料
型號(hào)： IS61SPS25632D-5TQ
廠商： INTEGRATED SILICON SOLUTION INC
元件分類(lèi)： SRAM
英文描述： 256K X 32 CACHE SRAM, 5 ns, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 2/22頁(yè)
文件大?。?/td> 152K
代理商： IS61SPS25632D-5TQ
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
04/17/01
IS61SPS25632T/D
IS61LPS25632T/D
IS61SPS25636T/D
IS61LPS25636T/D
IS61SPS51218T/D
IS61LPS51218T/D
ISSI
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
1,0
0,1
A1', A0' = 1,1
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under Bias
–40 to +85
°C
TSTG
Storage Temperature
–55 to +150
°C
PD
Power Dissipation
1.6
W
IOUT
Output Current (per I/O)
100
mA
VIN, VOUT Voltage Relative to GND for I/O Pins
–0.5 to VCCQ + 0.5
V
VIN
Voltage Relative to GND for
–0.5 to VCC + 0.5
V
for Address and Control Inputs
VCC
Voltage on Vcc Supply Relatiive to GND
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or
electric fields; however, precautions may be taken to avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
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