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參數(shù)資料
| 型號： | IS61S6432-5TQ |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| 中文描述： | 64K X 32 CACHE SRAM, 5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 140K |
| 代理商： | IS61S6432-5TQ |
PB
Integrated Silicon Solution, Inc.
1-800-379-4774
Rev.
B
06/28/01
IS61S6432
ISSI
TRUTH TABLE
Address
Used
Operation
CE1
CE2
CE3
ADSP
ADSC
ADV
WRITE
OE
DQ
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
1. All inputs except
OE
must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. "X" means don't care. WRITE=L means any one or more byte write enable signals (
BW1
-
BW4
) and
BWE
are LOW or
GW
is
LOW. WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation,
OE
must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5.
ADSP
LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or
more byte write enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of clock.
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
H
L
L
L
L
L
L
L
L
L
X
L
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
L
L
L
L
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
X
X
H
H
X
H
X
X
H
H
X
H
L
L
H
H
H
H
H
H
PARTIAL TRUTH TABLE
Function
GW
BWE
BW1
BW2
BW3
BW4
READ
READ
WRITE Byte 1
WRITE All Bytes
WRITE All Bytes
H
H
H
X
L
H
X
L
L
X
X
H
L
L
X
X
H
H
L
X
X
H
H
L
X
X
H
H
L
X
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