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參數(shù)資料
| 型號： | IS61S6432-5TQ |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| 中文描述： | 64K X 32 CACHE SRAM, 5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大小： | 140K |
| 代理商： | IS61S6432-5TQ |
PB
Integrated Silicon Solution, Inc.
1-800-379-4774
Rev.
B
06/28/01
IS61S6432
ISSI
READ CYCLE TIMING: PIPELINE
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE3
CE2
CE1
BW4-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
RD1
RD2
1a
2c
2d
3a
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE3 only sampled with ADSP or ADSC
CE1 Masks ADSP
Unselected with CE2
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQHZ
ADSC initiate read
ADSP is blocked by CE1 inactive
t
AVH
t
AVS
Suspend Burst
Pipelined Read
2a
2b
相關(guān)PDF資料 |
PDF描述 |
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| IS61S6432-5TQI | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61S6432-6PQ | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61S6432-6PQI | Octal D-Type Transparent Latches With 3-State Outputs 20-SSOP -40 to 85 |
| IS61S6432-6TQ | Octal D-Type Transparent Latches With 3-State Outputs 20-SSOP -40 to 85 |
| IS61S6432-6TQI | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
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