參數(shù)資料
型號(hào): IS61S6432-5PQ
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: Quadruple 2-Input Positive-OR Gates 14-TSSOP -40 to 85
中文描述: 64K X 32 CACHE SRAM, 5 ns, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 12/19頁(yè)
文件大?。?/td> 140K
代理商: IS61S6432-5PQ
PB
Integrated Silicon Solution, Inc.
1-800-379-4774
Rev.
B
06/28/01
IS61S6432
ISSI
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE3
CE2
CE1
BW4-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
WR1
WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE3 only sampled with ADSP or ADSC
CE1 Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE1 inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1
WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z
1a
3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
2b
2a
Write
2c
2d
相關(guān)PDF資料
PDF描述
IS61S6432-5PQI 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-5TQ 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-5TQI 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-6PQ 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-6PQI Octal D-Type Transparent Latches With 3-State Outputs 20-SSOP -40 to 85
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