參數(shù)資料
型號(hào): IS61C3216
廠商: Integrated Silicon Solution, Inc.
英文描述: 32K x 16 High-Speed CMOS Static RAM(32K x 16 高速CMOS靜態(tài)RAM)
中文描述: 32K的× 16高速CMOS靜態(tài)RAM(32K的× 16高速的CMOS靜態(tài)RAM)的
文件頁(yè)數(shù): 4/8頁(yè)
文件大小: 68K
代理商: IS61C3216
ISSI
IS61C3216
Integrated Silicon Solution, Inc.
SR007-1B
01/26/98
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-10
-12
-15
-20
Symbol
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
HZOE
(2)
t
LZOE
(2)
t
HZCE
(2
t
LZCE
(2)
t
BA
t
HZB
t
LZB
Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
Read Cycle Time
10
12
15
20
ns
Address Access Time
10
12
15
20
ns
Output Hold Time
3
3
3
3
ns
CE
Access Time
10
12
15
20
ns
OE
Access Time
5
5
7
8
ns
OE
to High-Z Output
0
5
0
6
0
7
8
ns
OE
to Low-Z Output
0
0
0
0
ns
CE
to High-Z Output
0
5
0
6
0
7
0
8
ns
CE
to Low-Z Output
4
4
4
4
ns
LB
,
UB
Access Time
5
6
7
8
ns
LB
,
UB
to High-Z Output
0
5
0
6
0
7
8
ns
LB
,
UB
to Low-Z Output
5
5
5
5
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured
±
500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1a and 1b
AC TEST LOADS
Figure 1a.
Figure 1b.
480
30 pF
Including
jig and
scope
255
OUTPUT
5V
480
5 pF
Including
jig and
scope
255
OUTPUT
5V
CAPACITANCE
(1)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
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