參數資料
型號: IS61C256AL-12TL
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 32K x 8 HIGH-SPEED CMOS STATIC RAM
中文描述: 32K X 8 STANDARD SRAM, 12 ns, PDSO28
封裝: LEAD FREE, PLASTIC, TSOP1-28
文件頁數: 6/12頁
文件大?。?/td> 107K
代理商: IS61C256AL-12TL
6
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
10/23/06
IS61C256AL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-10 ns
Min.
-12 ns
Min.
Symbol
t
WC
t
SCS
t
AW
Parameter
Max
Max.
Unit
Write Cycle Time
10
12
ns
CE
to Write End
9
10
ns
Address Setup Time
to Write End
9
10
ns
t
HA
Address Hold
from Write End
0
0
ns
t
SA
t
PWE
1
t
PWE
2
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Address Setup Time
0
0
ns
WE
Pulse Width (
OE
LOW)
9
9
ns
WE
Pulse Width (
OE
HIGH)
8
8
ns
Data Setup to Write End
7
7
ns
Data Hold from Write End
0
0
ns
WE
LOW to High-Z Output
6
6
ns
WE
HIGH to Low-Z Output
0
0
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
AC WAVEFORMS
WRITE CYCLE NO. 1 (
WE
Controlled)
(1,2)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCS
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
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