參數(shù)資料
型號(hào)： IS45S81600B
廠商： Integrated Silicon Solution, Inc.
英文描述： 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
中文描述： 16Meg × 8，8Meg x16 128兆位同步DRAM
文件頁(yè)數(shù)： 11/59頁(yè)
文件大?。?/td> 593K
代理商： IS45S81600B
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
04/14/06
11
ISSI
IS45S81600B, IS45S16800B
Current State
Write Recovering
CS
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
RAS
×
H
H
H
H
L
L
L
L
×
H
H
H
H
L
L
L
L
×
H
H
H
L
L
L
L
×
H
H
H
L
CAS
×
H
H
L
L
H
H
L
L
×
H
H
L
L
H
H
L
L
×
H
L
L
H
H
L
L
×
H
H
L
×
WE
×
H
L
H
L
H
L
H
L
×
H
L
H
L
H
L
H
L
×
×
H
L
H
L
H
L
×
H
L
×
×
Address
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
×
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
×
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
×
OC, BA
×
×
×
BA, CA, A10
BA, RA
Command
DESL
NOP
BST
READ/READA
WRIT/ WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP/BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
READ/WRITE
ACT/PRE/PALL
REF/MRS
Action
Nop, Enter row active after tDPL
Nop, Enter row active after tDPL
Nop, Enter row active after tDPL
Begin read
(8)
Begin new write
ILLEGAL
(3)
ILLEGAL
(3)
ILLEGAL
ILLEGAL
Nop, Enter precharge after tDPL
Nop, Enter precharge after tDPL
Nop, Enter row active after tDPL
ILLEGAL
(3,8,11)
ILLEGAL
(3,11)
ILLEGAL
(3,11)
ILLEGAL
(3,11)
ILLEGAL
ILLEGAL
Nop, Enter idle after tRC
Nop, Enter idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Nop, Enter idle after 2 clocks
Nop, Enter idle after 2 clocks
ILLEGAL
ILLEGAL
ILLEGAL
Write Recovering
with Auto
Precharge
Refresh
Mode Register
Accessing
FUNCTIONAL TRUTH TABLE Continued:
Note: H=V
IH
, L=V
IL
x= V
IH
or V
IL
, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will
be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will
be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks.
相關(guān)PDF資料
PDF描述
IS45S81600B-7TA 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
IS45S81600B-7TA1 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
IS45S81600B-7TLA 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
IS45S81600B-7TLA1 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS45S81600B-7TA 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
IS45S81600B-7TA1 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
IS45S81600B-7TLA 制造商:Integrated Silicon Solution Inc 功能描述:
IS45S81600B-7TLA1 制造商:Integrated Silicon Solution Inc 功能描述:
IS45S81600E 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16M x 8, 8M x16 128Mb SYNCHRONOUS DRAM
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