參數(shù)資料
型號: IS43R16160A-5TL
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 16Meg x 16 256-MBIT DDR SDRAM
中文描述: 16M X 16 DDR DRAM, 0.65 ns, PDSO66
封裝: LEAD FREE, PLASTIC, TSOP2-66
文件頁數(shù): 38/56頁
文件大?。?/td> 792K
代理商: IS43R16160A-5TL
38
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00B
11/28/05
ISSI
IS43R16160A
NOTES: (continued)
33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount.
34.
t
HP min is the lesser of
t
CL minimum and
t
CH minimum actually applied to the device CK and CK/ inputs,
collectively during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until
t
RAS(MIN) can be satisfied prior
to the internal precharge command being issued.
36. First DQS (LDQS or UDQS) to transition to last DQ (DQ0-DQ15) to transition valid.
Initial JEDEC specifications suggested this to be same as
t
DQSQ.
37. Normal Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage
will lie within the outer bounding lines of the V-I curve of Figure A.
b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but no
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A.
c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie
within the outer bounding lines of the V-I curve of Figure B.
d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be
between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage
and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device
drain-to-source voltages from 0.1V to 1.0 Volt.
38. Reduced Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage
will lie within the outer bounding lines of the V-I curve of Figure C.
b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure C.
c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie
within the outer bounding lines of the V-I curve of Figure D.
d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure D.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between
.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 V, and at the same voltage.
f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device
drain-to-source voltages from 0.1V to 1.0 V.
39. The voltage levels used are derived from the referenced test load. In practice, the voltage levels obtained from
a properly terminated bus will provide significantly different voltage values.
40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3
of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width < 3ns and the pulse width can not be greater than
1/3 of the cycle rate.
41. VDD and VDDQ must track each other.
42. Note 42 is not used.
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