參數(shù)資料
型號(hào): IS42VS16100C1-10T
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 1M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO50
封裝: 0.400 INCH, PLASTIC, MS-24, TSOP2-50
文件頁(yè)數(shù): 2/80頁(yè)
文件大?。?/td> 772K
代理商: IS42VS16100C1-10T
IS42VS16100C1
ISSI
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
04/15/05
PIN FUNCTIONS
Pin No.
Symbol
Type
Function (In Detail)
20 to 24
27 to 32
A0-A10
Input Pin
A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
command input and A0-A7 as column address inputs during read or write command
input. A10 is also used to determine the precharge mode during other commands. If
A10 is LOW during precharge command, the bank selected by A11 is precharged,
but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts
automatically after the burst access.
These signals become part of the OP CODE during mode register set command
input.
19
A11
Input Pin
A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when
high, bank 1 is selected. This signal becomes part of the OP CODE during mode
register set command input.
16
CAS
Input Pin
CAS
, in conjunction with the
RAS
and
WE
, forms the device command. See the
“Command Truth Table” item for details on device commands.
34
CKE
Input Pin
The CKE input determines whether the CLK input is enabled within the device. When
is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW,
invalid. When CKE is LOW, the device will be in either the power-down mode, the
clock suspend mode, or the self refresh mode. The CKE is an asynchronous input.
35
CLK
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
18
CS
Input Pin
The
CS
input determines whether command input is enabled within the device.
Command input is enabled when
CS
is LOW, and disabled with
CS
is HIGH. The
device remains in the previous state when
CS
is HIGH.
2, 3, 5, 6, 8, 9, 11
12, 39, 40, 42, 43,
45, 46, 48, 49
DQ0 to
DQ15
DQ Pin
DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units
using the LDQM and UDQM pins.
14, 36
LDQM,
UDQM
Input Pin
LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go
to the HIGH impedance state when LDQM/UDQM is HIGH. This function
corresponds to
OE
in conventional DRAMs. In write mode, LDQM and UDQM control
the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is
enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input
data is masked and cannot be written to the device.
17
RAS
Input Pin
RAS
, in conjunction with
CAS
and
WE
, forms the device command. See the
“Command Truth Table” item for details on device commands.
15
WE
Input Pin
WE
, in conjunction with
RAS
and
CAS
, forms the device command. See the
“Command Truth Table” item for details on device commands.
7, 13, 38, 44
VDDQ
Power Supply Pin
VDDQ is the output buffer power supply.
1, 25
VDD
Power Supply Pin
VDD is the device internal power supply.
4, 10, 41, 47
GNDQ
Power Supply Pin
GNDQ is the output buffer ground.
26, 50
GND
Power Supply Pin
GND is the device internal ground.
相關(guān)PDF資料
PDF描述
IS42VS16100C1-10TI 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16100C1-10TL 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10T 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-10TL 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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