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參數(shù)資料
| 型號： | IS42S32400B-6TL |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 中文描述： | 4M X 32 SYNCHRONOUS DRAM, 5.4 ns, PDSO86 |
| 封裝： | LEAD FREE, TSOP2-86 |
| 文件頁數(shù)： | 28/60頁 |
| 文件大?。?/td> | 644K |
| 代理商： | IS42S32400B-6TL |
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ISSI
28
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00G
06/15/06
IS42S32400B
possible CAS latency; data element
n
+ 3 is either the last of
a burst of four or the last desired of a longer burst. Following
the PRECHARGE command, a subsequent command to the
same bank cannot be issued until t
RP
is met. Note that part
of the row precharge time is hidden during the access of the
last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same opera-
tion that would result from the same fixed-length burst with
auto precharge. The disadvantage of the PRECHARGE
command is that it requires that the command and address
buses be available at the appropriate time to issue the
command; the advantage of the PRECHARGE command is
that it can be used to truncate fixed-length or full-page
bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST
TERMINATE command should be issued
x
cycles before
the clock edge at which the last desired data element is
valid, where
x
equals the CAS latency minus one. This is
shown in the READ Burst Termination diagram for each
possible CAS latency; data element
n
+ 3 is the last desired
data element of a longer burst.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS42S32400B-6TLI | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400B-7B | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400B-7BI | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400B-7BL | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400B-7BLI | 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S32400B-6TLI | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 86-Pin TSOP-II |
| IS42S32400B-6TL-TR | 功能描述:動態(tài)隨機(jī)存取存儲器 128M (4Mx32) 166MHz Commercial Temp RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS42S32400B-6T-TR | 制造商:Integrated Silicon Solution Inc 功能描述:IC SDRAM 128MBIT 166MHZ 86TSOP |
| IS42S32400B-7B | 制造商:Integrated Silicon Solution Inc 功能描述:IC SDRAM 128MBIT 143MHZ 90FBGA |
| IS42S32400B-7BI | 制造商:Integrated Silicon Solution Inc 功能描述:IC SDRAM 128MBIT 143MHZ 90FBGA |
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