參數(shù)資料
型號(hào)： IS42S32200C1-7TL
廠商： INTEGRATED SILICON SOLUTION INC
元件分類(lèi)： DRAM
英文描述： 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述： 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-86
文件頁(yè)數(shù)： 25/59頁(yè)
文件大小： 623K
代理商： IS42S32200C1-7TL
IS42S32200C1
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00E
05/18/06
25
CLK
CKE
HIGH - Z
COLUMN ADDRESS
AUTO PRECHARGE
BANK ADDRESS
CS
RAS
CAS
WE
A0-A7
A10
BA0, BA1
NO PRECHARGE
A8, A9
WRITE Command
The starting column and bank addresses are provided with
the WRITE command, and auto precharge is either enabled
or disabled for that access. If auto precharge is enabled, the
row being accessed is precharged at the completion of the
burst. For the generic WRITE commands used in the
following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid
data-in
element will be
registered coincident
with the
WRITE
command.
Subsequent
data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length
burst, assuming no other commands have been initiated,
the DQs will remain High-Z and any additional input data will
be ignored (see WRITE Burst). A full-page burst will
continue until terminated. (At the end of the page, it will wrap
to column 0 and continue.)
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-length
WRITE burst may be immediately followed by data for a
WRITE command. The new WRITE command can be issued
on any clock following the previous WRITE command, and
the data provided coincident with the new command applies
to the new command.
An example is shown in WRITE to WRITE diagram. Data
n
+ 1 is either the last of a burst of two or the last desired
of a longer burst. The 64Mb SDRAM uses a pipelined
architecture and therefore does not require the
2n
rule
associated with a prefetch architecture. A WRITE command
can be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses
within a page can be performed to the same bank, as
shown in Random WRITE Cycles, or each subsequent
WRITE may be performed to a different bank.
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-length
WRITE burst may be immediately followed by a subsequent
READ command. Once the READ com mand is regis-
tered, the data inputs will be ignored, and WRITEs will not
be executed. An example is shown in WRITE to READ.
Data
n
+ 1 is either the last of a burst of two or the last
desired of a longer burst.
Data for a fixed-length WRITE burst may be fol lowed by,
or truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page WRITE burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued t
WR
after the
clock edge at which the last desired input data element is
registered. The auto precharge mode requires a t
WR
of at
least one clock plus time, regardless of frequency. In
addition, when truncating a WRITE burst, the DQM signal
must be used to mask input data for the clock edge prior
to, and the clock edge coincident with, the PRECHARGE
command. An example is shown in the WRITE to
PRECHARGE diagram. Data
n
+1 is either the last of a burst
of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to the
same bank cannot be issued until t
RP
is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the opti-
mum time
(as described above)
provides the same operation
that would result from the same fixed-length burst with auto
precharge. The disadvantage of the
PRECHARGE
command
is that it requires that the command and address buses be
available at the appropriate time to issue the command; the
advantage of the PRECHARGE command is that it can be
used to truncate fixed-length or full-page bursts.
Fixed-length or full-page WRITE bursts can be truncated
with the BURST TERMINATE command. When truncating
a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last
data written (provided that DQM is LOW at that time) will
be the input data applied one clock previous to the BURST
TERMINATE command. This is shown in WRITE Burst
Termination, where data
n
is the last desired data element
of a longer burst.
WRITEs
WRITE bursts are initiated with a WRITE command, as
shown in WRITE Command diagram.
相關(guān)PDF資料
PDF描述
IS42S32200C1-7TLI 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200-6T 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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參數(shù)描述
IS42S32200C1-7TLI 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 64M 2Mx32 143Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線(xiàn)寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪(fǎng)問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S32200C1-7TLI-TR 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 64M 2Mx32 143Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線(xiàn)寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪(fǎng)問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S32200C1-7TL-TR 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 64M 2Mx32 143Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線(xiàn)寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪(fǎng)問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S32200C1-7T-TR 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 64M 2Mx32 143Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線(xiàn)寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪(fǎng)問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S32200E 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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